MFC2000 datasheet(95/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-65

4.5.3

Brief Timing

No matter which mode you use and which address you access, the DRAM access timing is lined up with the octal

halfword boundary.

SIUCLK

RASn[0]

CASEn[0]

ARM ADDR

or DMA ADDR

SIUADDR

EXTADDR

ROW

C O L

COL

R O W

COL

OCTAL

BOUNDARY

COL

a+2

a+4

NOTE: In this example, a =...01010, a+2=...01110, a+4=...10000

a+1

a+2

a+3

a+4

a+5

DWRn

DOEEn

DATA

Figure 4-18. 8-bit Memory Data Bus

The timing diagram illustrates an 8-bit memory data bus, a burst of halfword transfers (3 halfwords) from the

ARM7 or DMA, for ½ cycle CASn and PG = zero wait states (non-interleaved). It also illustrates the octal halfword

boundary that will cause the SIU to terminate the burst and cause the DRAM Controller to regenerate the RASn

precharge time. This interface speed can only be used at slow frequencies.

SIUCLK

RASn[1]

CASOn[1:0]

ARMADDR

SIUADDR

EXTADDR

ROW

C O L

COL

a+4

a+2

a+4

a+6

DWRn

DATA

DOEOn

Figure 4-19. 16-bit Memory Data Bus

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