MFC2000 datasheet(77/426 Pages) ETC

77 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-47

This section describes the three methods of interrupting the CPU program flow, which are:

•

Reset

•

Interrupts for the normal functions (IRQs)

•

Interrupt for the development system (through the IRQ16 pin)/Power Down (through the Power Down block)

The reset signal is controlled by the Prime Power Reset block. IRQs and SYSIRQn are managed by the Interrupt

Controller and are sent to the ARM as either an IRQ or a FIQ if enabled. Table 4-9 summarizes the interrupts and

their sources.

4.4.1.1

Reset

An active level on the CPU Reset input halts program execution and resets the CPU's internal registers. When the

CPU's Reset input is released, the CPU begins program execution at the address located in the reset vector. This

signal can be activated externally by putting low levels on the BATRSTn or RESETn pins, or internally by the

Watchdog Timer or the Battery Power Control logic Lockout circuitry. (For more information, see Section 5-1.)

4.4.1.2

System Interrupt

The system interrupt can be activated externally by the programmable interrupt IRQ16 or by the power down

signal from the Power Down Block. This interrupt is treated the same as other interrupts in the interrupt controller.

Firmware has the responsibility to make it the highest priority and to use it as the NMI function which is provided

by many other CPUs.

The input from the Power Down Block is detected and OR’ed with the programmable external IRQ16 pin. This

combined signal is then synchronized to the rising edge of SIUCLK, and then clocked to the falling edge of

SIUCLK before an interrupt will be operated in the interrupt controller.

For normal system operation, the system interrupt represents a loss of system power, indicated by Power Down

signal going low. The system interrupt control firmware performs the necessary power-down maintenance

operations, and then writes to the Lockout Enable register (LockEnn) to protect the battery backed-up registers

during loss of power. (Note that activating lockout also generates a reset).

4.4.1.3

Interrupts for Normal Functions

The level-mode interrupt is provided for internal and external interrupts. All internal interrupts are high-level

interrupts. The external Modem interrupt is a low-level interrupt. All other external interrupts are programmable to

be either high/low/level/edge interrupts. There are only two kinds of registers needed for the interrupt controller;

one is the interrupt enable register and another is the interrupt event register. The interrupt controller DOES NOT

prioritize the multiple sources of interrupts and DOES NOT generate the interrupt addresses. It only provides

interrupt masking for all of interrupts including the system interrupt (i.e., enable/disable control), and generates

the interrupt request for the CPU.

When the bit corresponding to an interrupt in the interrupt enable register is set, it enables the interrupt request to

cause an interrupt. When the bit is cleared, it masks the interrupt. When the event corresponding to an interrupt

bit in the interrupt event register occurs, this bit needs to be set on the rising edge of SIUCLK whether it is

enabled or not. On the falling edge of SIUCLK, the interrupt controller generates the interrupt (IRQn and FIQn) to

CPU. This interrupt controller has two identical sets of interrupt logic and registers for IRQn and FIQn. Firmware

needs to decide which interrupts trigger IRQn and which interrupts trigger FIQn. In the interrupt subroutine, the

CPU needs to clear the interrupt event from the interrupt source. Then, this bit will be reset at the following rising

edge of SIUCLK. For the software interrupt, the interrupt source is the interrupt bit in the interrupt event register

itself. Therefore, the CPU needs to write a 1 to generate the software interrupt and write a 0 to clear the software

interrupt.

The source of the IRQ is required to latch the interrupt signal and hold the signal active until the CPU processes

the IRQ. The CPU firmware clears the source of the IRQ before exiting the IRQ's service routine. If any IRQ's are

pending when new IRQ's are enabled by either setting the interrupt enable registers or the Interrupt Disable bit in

the CPU Processor Status register, the enabled IRQ causes an almost immediate CPU interrupt [the CPU only

acknowledges interrupts during the op code fetch of an instruction].

MFC2000 数据表(PDF) 77 Page - List of Unclassifed Manufacturers

MFC2000 数据表(HTML) 77 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载