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MFC2000 数据表(PDF) 80 Page - List of Unclassifed Manufacturers

部件名 MFC2000
功能描述  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

MFC2000 数据表(HTML) 80 Page - List of Unclassifed Manufacturers

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MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
4-50
Conexant
100723A
4.4.2.2
IRQ/FIQ Event2 Register
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
IRQFIQEvent2
0x01FF8023
(Not
Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
Rst Value
xxh
Read Value
00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
IRQFIQEvent2
0x01FF8022
(Not
Used)
IRQ22
irqusb
Event
Status
IRQ21
irqtimer2
Event
Status
IRQ20
irqsdaa
Event
Status
IRQ19
irqdma5
Event
Status
IRQ18
irqssif
Event
Status
IRQ17
irqsw
Event
Status
IRQ16
irqsys
Event
Status
Rst Value
x0000000b
Read Value
00h
Bit 6
Internal USB interrupt from USB block. Read only.
Bit 5
Internal timer 2 interrupt up to 50 ms. Read only.
Bit 4
Internal SmartDAA interface interrupt from SmartDAA IF block. Read
only.
Bit 3
Internal DMA channel 5 interrupt from DMA controller block. Read
only.
Bit 2
Internal SSIF from SSIF block. Read only.
Bit 1
Internal Software interrupt. When CPU writes a 1, the software
interrupt is issued. When CPU writes a 0, the software interrupt is
cleared. R/W.
Bit 0
Internal system interrupt from programmable external interrupt 16 or
power down circuit Read only.
4.4.2.3
IRQ Enable1 Register
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
IRQEnable1
0x01FF8025
Enable
IRQ15
irqsopif
Enable
IRQ14 irqt4
Enable
IRQ13
irqext2
Enable
IRQ12
irqpio
Enable
IRQ11
irqext1
Enable
IRQ10
irqtimer1
Enable
IRQ9
irqvsc
Enable
IRQ8
irqdma10
Rst Value
00h
Read Value
00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
IRQEnable1
0x01FF8024
Enable
IRQ7
irqbrc
Enable
IRQ6
irqdma2
Enable
IRQ5
irqsasif
Enable
IRQ4
irqvpstep
Enable
IRQ3
irqsstep
Enable
IRQ2
irqprt
Enable
IRQ1
irqcbs
Enable
IRQ0 MIRQ
Rst Value
00h
Read Value
00h
Bit 15 – 0:
When 1 will enable the corresponding interrupt and when 0 will mask
that interrupt out. R/W.



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