MFC2000 datasheet(97/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-67

This example illustrates a read of two-way interleaved memory with halfword bursts of data (6 halfwords). It also

illustrates that the octal halfword boundary doesn’t occur in the middle of the burst of halfword transfers. It

assumes external drivers to minimize the data bus contention and to insure that the data has enough setup time

to CLK. This waveform also illustrates, increased RASn precharge time and increased address multiplexing time.

Byte bursts of data are not allowed when a 16-bit memory structure is used.

SIUCLK

RASn[0]

CASEn[1:0]

DWRn

ARM ADDR

SIU ADDR

EXT ADDR

a+4

ROW

COL

DATA

DOEOn

DOEEn

CASOn[1:0]

SIU P_ADDR

COL

+10

a+8

+10

Figure 4-22. 2-Way Interleaved DRAM Read (3 words)

The timing diagram illustrates a two-way interleaved DRAM read (3 words). It assumes external drivers to

minimize the data bus contention and to insure that the data has enough setup time to CLK. This waveform also

illustrates, increased RASn precharge time and increased address multiplexing time.

SIUCLK

RASn[1]

CASEn[1:0]

DWRn

ARM ADDR

SIU ADDR

EXT ADDR

a+4

a+8

ROW

COL

a+4

a+8

COL

a+2

a+6

a+10

DATA

DOEOn

DOEEn

CASOn[1:0]

COL

Figure 4-23. 2-Way Interleaved DRAM Write

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