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MFC2000 数据表(PDF) 90 Page - List of Unclassifed Manufacturers

部件名 MFC2000
功能描述  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

MFC2000 数据表(HTML) 90 Page - List of Unclassifed Manufacturers

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MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
4-60
Conexant
100723A
DRAM
DRAM
DRAM
ASIC
Q-
Switch
Q-
Switch
DWRn
CASEn[0]
CASEn[1]
CASOn[0]
CASOn[1]
DWRn
RASn[0]
addr[11:0]
RASn[0]
addr[11:0]
addr[u:0]
data[7:0]
RASn[1]
CASOn[0]
DWRn
DOEOn (Wron)
data[15:0]
data[15:0]
Bank 0
(Interleaved)
Bank 1
(8-bit
Non-interleaved)
WEn
OEn
OEn
WEn
DOEOn (WRon)
DOEen (WRen)
OEn
WEn
Figure 4-17. DRAM Interface Example
Figure 4-17 gives an example of how each bank of DRAMs might be setup for non-battery back-up DRAM
system. In this example, Bank 0 is setup for an 8-bit non-interleaved memory bank and Bank 1 is setup with a 16-
bit 2-way interleaved DRAM bank.
Note:
1.
DWRn is a battery backed-up signal and is ‘high’ during the battery back-up mode. All inputs
of the prime powered logic will have ‘no power’ or ‘low’ during the battery back-up mode.
Therefore, all external logic, which uses DWRn, should be battery backed-up logic and
should be gated with WRPROTn to ensure that outputs are ‘low’ when the prime power is off
for the battery back-up DRAM operation.
2.
DWRn, CASO[1:0]n and CASE[1:0]n are shared by both DRAM banks (RAS[0]n and
RAS[1]n). If you only want to back up one bank by battery power, all shared signals should
be separated by the external logic and should follow the rule in note 2.



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