MFC2000 datasheet(49/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-19

4.2

Cache Memory Controller

4.2.1

Functional Description

4.2.1.1

Cache Summary

•

4 kB instruction cache RAM with expansion capability

•

Physical address cache access and cache tags

•

Two Way Set Associative with LRU algorithm

•

16 bytes cache line size with 128 cache lines in each way

•

Supports both ARM and thumb mode instructions

•

Cache memory can be enabled or disabled

•

Provides lock function and flush function

•

Interfaces between ARM7TDMI and SIU (System Interface Unit)

4.2.1.2

Cache Overview

The Cache Controller is an instruction only cache; a level 1 cache for ARM7TDMI. The cache, when enabled, will

support zero wait state sequential instruction access from ARM provided the instruction is in the cache and valid

(Cache hit). If an instruction is not found in the cache memory (Cache miss), the Cache Controller will activate the

LRU (Least Recently Used) replacement algorithm. In this case, the ARM will incur a number of wait states

depending on the memory speed.

The 4 kB Cache Memory is divided into two Ways, which means 2 kB per Way. Each Way is further divided into

128 Cache Lines with 16 bytes of instructions in each Line. If a Cache miss is detected and Cache Line fill is

required, the Cache Controller will replace the least recently used (LRU) Cache line, the Cache Line fill operation

is done in burst (sequential), minimizing the overhead.

The ability for the software to lock the entire Cache or individual line and to flush the entire Cache Memory

contents are provided. In addition, the Cache Memory and Cache Tags can be placed in Test Mode for power-up

verification and system diagnoses. The entire Cache Memory and Cache Controller can also be disabled allowing

the ARM to bypass the Cache Controller unit.

Cache

RAM

( 2K

Bytes )

Cache Tag

(128 Sets)

a[31 : 11]

21 bits

1 bit

32 bits

16 bytes

Way

1 bit

Figure 4-3. MFC2000 Cache Organization

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