MFC2000 datasheet(111/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-81

SIUCLK

Ext. DMAACK

DMA address

Ext. address bus

DMA data

Ext. data bus

Ext. DMAREQ

tDRS

tAD

tDADN

tDOH

tWD

tDADF

WREn

DMA Cycle

tWD

Figure 4-33. External DMA Write Timing (Single Access, One Wait State)

Parameter

Symbol

Min

Max

Units

RDn delay (ext. load = 50pF)

tRD



WRn delay (ext. load = 50pF)

tWD



Address delay (ext. load = 50pF)

tAD



DMAACK on delay time (ext. load = 15pF)

tDADN



DMAACK off delay time (ext. load = 15pF)

tDADF



5ns

DMA Input Data Hold

tDIH



DMA Output Data Hold (ext. load = 50pF)

tDOH

RASn delay (ext. load = 40pF)

tRASD



CASn delay (ext. load = 40pF)

tCASD



DWRn delay (ext. load = 40pF)

tDWD

-20

Notes:

SIUCLK is the internal system interface clock. These values is for SIUCLK = 30 MHz.

The external DMA request set-up time (tDRS) is not required because this input is double

synchronized internally for the meta-stable case.

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