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AD7687

Data Sheet

Rev. E | Page 14 of 26

THEORY OF OPERATION

SW+

MSB

16,384C

IN+

LSB

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

REF

GND

IN–

32,768C

SW–

MSB

16,384C

LSB

32,768C

Figure 24. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7687 is a fast, low power, single-supply, precise 16-bit

ADC using a successive approximation architecture.

The AD7687 is capable of converting 250,000 samples per

second (250 kSPS) and powers down between conversions.

When operating at 100 SPS, for example, it typically consumes

1.35 µW, which is ideal for battery-powered applications.

The AD7687 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple multiplexed channel applications.

The AD7687 is specified for use from 2.3 V to 5.5 V and can be

interfaced to any of the 1.8 V to 5 V digital logic family. It is

housed in a 10-lead MSOP or in a tiny 10-lead LFCSP that saves

space and allows flexible configurations.

It is pin-for-pin-compatible with the AD7685, AD7686, and

AD7688.

CONVERTER OPERATION

The AD7687 is a successive approximation ADC based on a

charge redistribution DAC. Figure 24 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via SW+ and

SW−. All independent switches are connected to the analog

inputs. Thus, the capacitor arrays function as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs. When the acquisition phase is complete and the CNV

input goes high, a conversion phase is initiated. When the

conversion phase begins, SW+ and SW− open first. The two

capacitor arrays are then disconnected from the inputs and

connected to the GND input. Therefore, the differential voltage

between the inputs IN+ and IN− captured at the end of the

acquisition phase is applied to the comparator inputs, causing

the comparator to become unbalanced. By switching each

element of the capacitor array between GND and REF, the

comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4…VREF/65536). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

into a balanced condition. After the completion of this process,

the device returns to the acquisition phase and the control logic

generates the ADC output code and a BUSY signal indicator.

Because the AD7687 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

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