Data Sheet

AD7687

Rev. E | Page 21 of 26

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7687 devices are

connected to an SPI-compatible digital host.

Figure 38 shows a connection diagram example using two

AD7687 devices and Figure 39 gives the corresponding timing.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback (if SDI and CNV are low, SDO is

driven low). Prior to the minimum conversion time, SDI can be

used to select other SPI devices, such as analog multiplexers,

but SDI must be returned high before the minimum conversion

time and held high until the maximum conversion time to

avoid the generation of the BUSY signal indicator. When the

conversion is complete, the AD7687 enters the acquisition

phase and powers down. Each ADC result can be read by

bringing low its SDI input, which consequently outputs the

MSB onto SDO. The remaining data bits are then clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can capture the data, a digital

host using the SCK falling edge allows a faster reading rate

(provided it has an acceptable hold time). After the 16th SCK

falling edge, or when SDI goes high, whichever is earlier, SDO

returns to high impedance and another AD7687 can be read.

DATA IN

CLK

CS1

CONVERT

CS2

DIGITAL HOST

CNV

SCK

SDO

SDI

AD7687

CNV

SCK

SDO

SDI

AD7687

Figure 38. CS Mode, 4-Wire Without BUSY Indicator Connection Diagram

SDO

D15

D14

D13

D1

D0

SCK

1

2

3

30

31

32

CONVERSION

ACQUISITION

ACQUISITION

SDI(CS1)

CNV

D1

14

15

D0

D15

D14

17

18

16

SDI(CS2)

Figure 39. CS Mode, 4-Wire Without BUSY Indicator Serial Interface Timing