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AD7687BCPZ-R2 数据表(PDF) 24 Page - Analog Devices

部件名 AD7687BCPZ-R2
功能描述  16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP
PDF  27 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7687BCPZ-R2 数据表(HTML) 24 Page - Analog Devices

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Data Sheet
AD7687
Rev. E | Page 23 of 26
CHAIN MODE WITHOUT BUSY INDICATOR
Use this mode to daisy-chain multiple AD7687 devices on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for isolated
multiconverter applications, or for systems with a limited
interfacing capacity (for example). Data readback is analogous
to clocking a shift register.
Figure 42 shows a connection diagram example using two
AD7687 devices and Figure 43 gives the corresponding timing.
When SDI and CNV are low, SDO is driven low. With SDI and
SCK low, a rising edge on CNV initiates a conversion, selects
the chain mode, and disables the BUSY indicator. In this mode,
CNV is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7687 enters the acquisition phase
and powers down. The remaining data bits stored in the
internal shift register are then shifted out by subsequent SCK
falling edges. For each ADC, SDI feeds the input of the internal
shift register; these data bits are also shifted in by the SCK
falling edge. Each of the N ADCs in the chain outputs its data
MSB first. The data is valid on both SCK edges. Although the
rising edge can capture the data, a digital host using the SCK
falling edge allows a faster reading rate and, consequently, more
AD7687 devices in the chain (provided the digital host has an
acceptable hold time). After the 16 × Nth SCK falling edge or
CNV rising edge, whichever is earlier, SDO is driven low again.
The maximum conversion rate can be reduced due to the total
readback time. For example, using a digital host with a 3 ns set-
up time and 3 V interface, up to eight AD7687 devices daisy-
chained on a 3-wire port can be run at a maximum effective
conversion rate of 220 kSPS.
CLK
CONVERT
DATA IN
DIGITAL HOST
CNV
SCK
SDO
SDI
AD7687
B
CNV
SCK
SDO
SDI
AD7687
A
Figure 42. Chain Mode Without BUSY Indicator Connection Diagram
SDOA = SDIB
DA15
DA14
DA13
SCK
1
2
3
30
31
32
tSSDISCK
tHSDISC
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
14
15
tSCK
tSCKL
tSCKH
DA0
17
18
16
SDIA = 0
SDOB
DB15
DB14
DB13
DA1
DB1
DB0
DA15
DA14
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
Figure 43. Chain Mode Without BUSY Indicator Serial Interface Timing



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