AD7687BCPZ-R2 datasheet(23/27 Pages) AD

23 / 27 page

AD7687

Data Sheet

Rev. E | Page 22 of 26

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7687 is connected to

an SPI-compatible digital host, which has an interrupt input, and it

is desired to keep CNV, which is used to sample the analog input,

independent of the signal used to select the data reading. This

requirement is particularly important in applications where low

jitter on CNV is desired.

Figure 40 shows the connection diagram and Figure 41 gives

the corresponding timing.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback (if SDI and CNV are low, SDO is

driven low). Prior to the minimum conversion time, SDI can

select other SPI devices, such as analog multiplexers, but SDI

must be returned low before the minimum conversion time and

held low until the maximum conversion time to guarantee the

generation of the BUSY signal indicator. When the conversion

is complete, SDO goes from high to low impedance. With a

pull-up on the SDO line, this transition can act as an interrupt

signal to initiate the data readback controlled by the digital host.

When using this option, select the value of the pull-up resistor

such that it maintains an appropriate rise time on the SDO line

for the application. This is a function of the resistance of the

pull-up and the capacitance of the SDO line. The AD7687 then

enters the acquisition phase and powers down. The data bits are

then clocked out, MSB first, by subsequent SCK falling edges.

The data is valid on both SCK edges. Although the rising edge

can capture the data, a digital host using the SCK falling edge

allows a faster reading rate (provided it has an acceptable hold

time). After the optional 17th SCK falling edge, or SDI going

high, whichever is earlier, the SDO returns to high impedance.

DATA IN

IRQ

CLK

CONVERT

CS1

VIO

DIGITAL HOST

47k



CNV

SCK

SDO

SDI

AD7687

Figure 40. CS Mode, 4-Wire with BUSY Indicator Connection Diagram

SDO

D15

D14

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI

CNV

tSSDICNV

tHSDICNV

Figure 41. CS Mode, 4-Wire with BUSY Indicator Serial Interface Timing

AD7687BCPZ-R2 数据表(PDF) 23 Page - Analog Devices

AD7687BCPZ-R2 数据表(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

数据表下载