AD7687BCPZ-R2 datasheet(19/27 Pages) AD

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AD7687

Data Sheet

Rev. E | Page 18 of 26

Additionally, it is resistant to power supply variations over a wide

frequency range. Figure 31 shows the power supply rejection

ration (PSRR) of the device over frequency.

FREQUENCY (kHz)

100

1000

10000

VDD = 5V

VDD = 2.5V

Figure 31. PSRR vs. Frequency

The AD7687 powers down automatically at the end of each

conversion phase, and consequentially its power consumption

scales linearly with the sampling rate, as shown in Figure 32.

This makes the device ideal for low sampling rate (even a few

SPS) and low battery-powered applications.

SAMPLING RATE (SPS)

1000

0.1

0.001

100

1000

10000

100000

1000000

VIO

VDD = 5V

VDD = 2.5V

Figure 32. Operating Currents vs. Sampling Rate

SUPPLYING THE ADC FROM THE REFERENCE

With its low operating current, the AD7687 can be supplied

directly by the reference circuitry (see Figure 33). The reference

line is driven by one of the following:



The system power supply directly.



A reference voltage with enough current output capability,

such as the ADR435.



A reference buffer, such as the AD8031, which can also

filter the system power supply (see Figure 33).

AD8031

AD7687

VIO

REF

VDD

F



10k



F

1OPTIONAL REFERENCE BUFFER AND FILTER.

Figure 33. Example of Application Circuit

DIGITAL INTERFACE

Though the AD7687 has a reduced number of pins, it offers

flexibility in its serial interface modes.

When in CS mode, the AD7687 is compatible with SPI, QSPI,

digital hosts, and DSPs, such as the Blackfin® processors or the

high performance, mixed-signal DSP family. In this mode, the

AD7687 uses either a 3-wire or a 4-wire interface. A 3-wire

interface using the CNV, SCK, and SDO signals minimizes

wiring connections and is useful, for instance, in isolated

applications. A 4-wire interface using the SDI, CNV, SCK, and

SDO signals allows CNV, which initiates the conversions, to be

independent of the readback timing (SDI). This is useful in low

jitter sampling or simultaneous sampling applications.

When in chain mode, the AD7687 provides a daisy chain

feature using the SDI input for cascading multiple ADCs on a

single data line similar to a shift register.

The mode in which the device operates depends on the SDI

level when the CNV rising edge occurs. The CS mode is

selected if SDI is high, and the chain mode is selected if SDI is

low. The SDI hold time is such that when SDI and CNV are

connected together, the chain mode is always selected.

The initial state of SDO on power up is indeterminate. Therefore,

to put SDO in a known state, initiate a conversion and clock out

all data bits.

In either mode, the AD7687 offers the option of forcing a start

bit in front of the data bits. Use this start bit as a BUSY signal

indicator to interrupt the digital host and trigger the data

reading. Otherwise, without a BUSY indicator, the user must

time out the maximum conversion time prior to readback.

The BUSY indicator feature is enabled



In the CS mode if CNV or SDI is low when the ADC

conversion ends (see Figure 37 and Figure 41).



In the chain mode if SCK is high during the CNV rising

edge (see Figure 45).

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