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AC104X-DS00-R 数据表(PDF) 25 Page - Broadcom Corporation. |
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AC104X-DS00-R 数据表(HTML) 25 Page - Broadcom Corporation. |
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25 / 50 page ![]() Preliminary Data Sheet ■ AC104X 12/11/01 B roa dcom Co rpo rat ion Document AC104X-DS00-405-R Section 3: Register Descriptions Page 17 Table 11: Registers 8-31 Register Description Default 8-15 Reserved XXXX 16 BT and Interrupt Level Control Register 1000 17 Interrupt Control/Status Register 0000 18,19 Reserved XXXX 20 Cable measurement Capability Register XXXX 21 Receive Error Counter Register 0000 22-31 Reserved XXXX Table 12: Register 0: Control Bit Name Description Mode Default 0.15 Reset 1 = PHY reset. This bit is self-clearing. RW/SC 0 0.14 Loopback 1 = Enable loopback mode. This loopbacks the TXD to RXD and ignores all the activity on the cable media. 0 = Normal operation. RW 0 0.13 Speed Select 1 = 100 Mbps 0 = 10 Mbps. AutoNeg enabled: This bit is writable but will be ignored. RW Set by FORC100 pin 0.12 ANeg Enable 1 = Enable Auto-Negotiate process (overrides 0.13 and 0.8) 0 = Disable Auto-Negotiate process. Mode selection is controlled via bit 0.8, 0.13 or through the mode pins. RW Set by ANEGA 0.11 Power Down 1 = Power down. All blocks except for SMI turns off. Setting PWRDN pin to high achieves the same result. 0 = Normal operation. RW 0 0.10 Isolate 1 = Electrically isolate the PHY from MII. PHY is still able to response to SMI. 0 = Normal operation. RW 0.9 Restart ANeg 1 = Restart Auto-Negotiation process. 0 = Normal operation. RW/SC 0 0.8 Duplex Mode 1 = Full-duplex. 0 = Half-duplex. AutoNeg enabled: This bit is writable but will be ignored. The default value is 0 if auto-negotiation is enabled via pin ANEGA. RW Set by DPLX and ANEGA pin 0.7 Collision Test 1 = Enable collision test, which issues the COL signal in response to the assertion of TX_EN signal. Collision test is disabled if PCSBP pin is high. Collision test is enabled regardless of the duplex mode. 0 = Disable COL test. RW 0 0.[6:0] Reserved RW 0000000 |
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