Preliminary Data Sheet

12/11/01

B roa dcom Co rpo rat ion

Document

AC104X-DS00-405-R

Section 1: Functional Description

10BASE-T/100BASE-TX

The multi-mode driver transmits the MLT-3 coded signal in 100BASE-TX mode and Manchester coded signal in 10BASE-T

mode.

In 10BASE-T mode, high frequency pre-emphasis is performed to extend the cable-driving distance without the external

filter. The FLP and NLP pulses are also drive out through the 10BASE-T driver.

The 10BASE-T and 100BASE-TX transmit signals are multiplexed to the transmit output driver. This arrangement results in

using the same external transformer for both the 10BASE-T and the 100BASE-TX. The driver output level is set by a built-

in bandgap reference and an external resistor connected to the IBREF pin. The resistor sets the output current for all modes

of operation. The TXOP/N outputs are open drain devices with a serial source to I/O pad resistance of 10 W max. When the

1:1 transformer is used, the current rating is 40 mA for the 2Vp-p MLT-3 signal, and 100 mA for the 5Vp-p Manchester signal.

One can use a 1.25:1 transmit transformer for a 20% output driver power reduction. This will decrease the drive current to

32 mA for 100BASE-TX operation, and 80 mA for 10BASE-T operation.

The PHY is designed to accommodate a maximum of 150 meters UTP CAT-5 cable. An AT&T 1061 CAT-5 cable of this

length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst case

cable attenuation is around 24-26 dB as defined by TP-PMD specification.

The amplitude and phase distortion from the cable cause inter-symbol interference (ISI) which makes clock and data

recovery difficult. The adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable.

The equalizer has the ability to changes its equalizer frequency response according to the cable length. The equalizer will

tune itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable.

The PHY includes an on-chip PLL clock synthesizer that generates a 125 MHz clocks for the 100BASE-TX circuitry. It also

generates 20 MHz and 100 MHz clocks for the 10BASE-T and ANeg circuitry. The PLL clock generator uses a fully

differential VCO cell that introduces very low jitter. The Zero Dead Zone Phase Detection method implemented in the PHY

design provides excellent phase tracking. A charge pump with charge sharing compensation is also included to further

reduce jitter at different loop filter voltages. The on-chip loop filter eliminates the need for external components and

minimizes the external noise sensitivity. Only one external 50 MHz crystal or clock source is required as a reference clock.

After power-on or reset, the PLL clock synthesizer generates the 20 MHz clock output until the 100BASE-X operation mode

is selected.

After the MAC transmitter exceeds the jabber timer (46mS), the transmit and loopback functions will be disabled and COL

signal get asserted. After TX_EN goes low for more than 500 ms, the TP transmitter will reactivate and COL gets de-

asserted. Setting Jabber Disable will disable the jabber function.

When the SQE test is enabled, a COL pulse with 5-15BT is asserted after each transmitted packet. SQE is enabled in

10BASE-T by default, and can be disabled via SQE Test Inhibit.