Preliminary Data Sheet

12/11/01

B roa dcom Co rpo rat ion

Document

AC104X-DS00-405-R

Section 1: Functional Description

Register 4 contains the current capabilities, speed and duplex, of the PHY, determined through hardware selects or chip

defaults. The contents of Reg. 4 is sent to its link partner during the ANeg process using Fast Link Pulses (FLPs). An FLP

is a string of 1s and 0s, each of which has a particular meaning, the total of which is called a Link Code Word. After reset,

software can change any of these bits from 1 to 0 and back to 1, but not from 0 to 1. Therefore, the hardware has priority

over software.

When ANeg is enabled, the PHY sends out FLPs during the following conditions:

•

Power on

•

Link loss

•

Restart ANeg command by software

During this period, the PHY continually sends out FLPs while monitoring the incoming FLPs from the link partner to

determine their optimal mode of operation. If FLPs are not detected during this phase of operation, Parallel Detection mode

is entered (see below).

When the PHY receives 3 identical link code words (ignoring acknowledge bit) from its link partner, it stores these code words

in Reg. 5, sets the acknowledge bit it the generated FLPs, and waits to receive 3 identical code word with the acknowledge

bit set from the link partner. Once this occurs the PHY configures itself to the highest technology that is common to both

ends. The technology priorities are:

1

100BASE-TX, full-duplex

2

100BASE-TX, half-duplex

3

10BASE-T, full-duplex

4

10BASE-T half-duplex.

Once the ANeg is complete, Reg. 1.5 is set, Reg. 1.[14:11] reflects negotiated speed and duplex mode, and the PHY enters

the negotiated transmission and reception state. This state will not change until link is lost or the PHY is reset through either

hardware or software, or the restart negotiation bit (Reg. 0.9) is set.

Because there are many devices in the field that do not support the ANeg process, but must still be communicated with, it

is necessary to detect and link through the Parallel Detection process.

The parallel detection circuit is enabled in the absence of FLPs. The circuit is able to detect:

•

Normal Link Pulse (NLP)

•

10BASE-T receive data

•

100BASE-TX idle

The mode of operation gets configured based on the technology of the incoming signal. If any of the above is detected, the

device automatically configures to match the detected operating speed in the half-duplex mode. This ability allows the device

to communicate with the legacy 10BASE-T and 100BASE-TX systems, while maintaining the flexibility of Auto-Negotiation.