Preliminary Data Sheet

12/11/01

B roa dcom Co rpo rat ion

Section 1: Functional Description

Document

AC104X-DS00-405-R

Certain cable plants have crossed wiring on the twisted pairs; the reversal of TXIN and TXIP. Under normal circumstances

this would cause the receive circuitry to reject all data. When the Auto Polarity Disable bit is cleared, the PHY has the ability

to detect the fact that either 8 NLPs or a burst of FLPs are inverted and automatically reverse the receiver's polarity. The

polarity state is stored in the Reverse Polarity bit.

If the Auto Polarity Disable bit is set, then the Reverse Polarity bit can be written to force the polarity reversal of the receiver.

Several different states of operation can be chosen through hardware configuration. External pins may be pulled either high

or low at reset time. The combination of high and low values determines the power on state of the device.

Many of these pins are multi-function pins which change their meaning when reset ends.

Several different states of operation can be chosen through software configuration. Please refer to the ”SMI” on page 1 as

well as Section 3 ”Register Descriptions” on page 16.

Each of the 4 ports has 3 individual LED outputs available to indicate Speed, Duplex/Collision, and Link/Activity. These multi-

function pins are inputs during reset and LED output pins thereafter. The level of these pins during reset determines their

active output states. If a multi-function pin is pulled up during reset to select a particular function, then that LED output would

become active low, and the LED circuit must be designed accordingly, and vice versa.

By definition the 10/100 Transceiver is able to run at either 10Mbps or 100Mbps. In addition the PHY is able to run in either

half-duplex or full-duplex. To determine the operational state, the PHY has hardware selects and software selects while also

supporting Auto- Negotiation and Parallel Detection.

Legitimate operating states are:

•

10BASE-T half-duplex

•

10BASE-T full-duplex

•

100BASE-TX half-duplex

•

100BASE-TX full-duplex

The PHY can be hardware configured to force any one of the above mentioned modes. By forcing the mode, the PHY will

only run in that mode, hence limiting the locations where the product will operate.

The PHY is able to negotiate its mode of operation using the Auto-Negotiation mechanism defined in the clause 28 of IEEE

802.3u specification. ANeg can be enabled or disabled by hardware (ANEGA pin) or software (Reg. 0.12) control. When

the ANeg is enabled, the PHY chooses its mode of operation by advertising its abilities and comparing them with the ability

received from its link partner. It can be configured to advertise 100BASE-TX or 10BASE-T operating in either full- or half-

duplex.