Preliminary Data Sheet

12/11/01

B roa dcom Co rpo rat ion

Document

AC104X-DS00-405-R

Section 1: Functional Description

Sect ion 1 : F un cti o n a l Descrip t io n

The AC104X physical layer device (PHY) integrates the 100BASE-TX and 10BASE-T functions in a single four port chip that

is used in Fast Ethernet 10/100 Mbps applications. The 100BASE-TX section consists of PCS, PMA, and PMD functions

and the 10BASE-T section is consisted of Manchester ENDEC and transceiver functions. The device performs the following

functions:

•

4B/5B

•

MLT3

•

NRZI

•

Manchester Encoding and Decoding

•

Clock and Data Recovery

•

Stream Cipher Scrambling / De-Scrambling

•

Adaptive Equalization

•

Line Transmission

•

Carrier Sense

•

Link Integrity Monitor

•

Auto-Negotiation (ANeg)

•

Auto-MDI/MDIX

•

RMII MAC connectivity

•

MII Management Function

It also provides an RMII consortium compatible Reduced Media Independent Interface (RMII) to communicate with an

Ethernet Media Access Controller (MAC). Selection of 10 or 100 Mbps operation is based on the settings of internal Serial

Management Interface registers or determined by the on-chip ANeg logic. The device can operate in 10 or 100 Mbps with

full-duplex or half-duplex mode on a per-port basis.

RMII

The Reduced Media Independent Interface (RMII) is used to connect the PHY with the MAC. The PHY and MAC obtain their

clock from a common 50 MHz source, such as a clock oscillator. This clock is shared by all ports within the PHY for

transmitting and receiving data on 2 individual 2-bit data buses. In 100M mode, RXD[1:0] is sampled on every cycle of

REFCLK. In 10M mode, RXD[1:0] is sampled on every 10th cycle of REFCLK. RXER is generated by the PHY to indicate a

receive error to the MAC.

TX_EN is generated by the MAC to indicate to the PHY when there is valid data on the transmit

bus. In 100M mode, the PHY will read 2 bits from TXD[1:0] for each cycle of REFCLK. In 10M mode, the PHY will read 2

bits of data from TXD[1:0] every 10th cycle of REFCLK.

The Serial Management Interface (SMI) is shared between all ports in the PHY. This totals 7 pins per port plus 3 per PHY.

SMI

The PHY's internal registers are accessible only through the MII 2-wire Serial Management Interface (SMI). MDC is a clock

input to the PHY, which is used to latch in or out data and instructions for the PHY. The clock can run from 2.5MHz to 25

MHz. MDIO is a bi-directional connection used to write instructions to, write data to, or read data from the PHY. Each data

bit is latched either in or out on the rising edge of MDC. MDC is not required to maintain any speed or duty cycle, provided

no half cycle is less than 20ns and that data is presented synchronous to MDC.