Preliminary Data Sheet

12/11/01

B roa dcom Co rpo rat ion

Section 1: Functional Description

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AC104X-DS00-405-R

MDC/MDIO are a common signal pair to all ports on a design. Therefore, each port needs to have its own unique Physical

Address. The Physical Address of the PHY is set using the pins defined as PHYAD[4:2]. These input signals are strapped

externally and sampled as reset is negated. PHYAD[1:0] are addressed for each port internal to the PHY. Internal addresses

are either 00, 01, 10, 11 or 01, 10, 11, 00 depending on the polarity of PHYAD_ST during reset.

At idle, the PHY is responsible to pull MDIO line to a high state. Therefore, a 1.5K Ohm resistor is used to pull the MDIO

signal high. The PHYAD can be reprogrammed via software. A detailed definition of the Serial Management registers can

be found in the next section.

At the beginning of a read or write cycle, the MAC will send a continuous 32 bits of one at the MDC clock rate to indicate

preamble. A zero and a one will follow to indicate start of frame. A read OP code is a one and a zero, while a write OP code

is a zero and a one. These will be followed by 5 bits to indicate PHY address and 5 bits to indicate register address. Then 2

bits follow to allow for turn around time. For read operation, the first bit will be high impedance. Neither the PHY nor the

station will assert this bit. During the second bit time, the PHY will assert this bit to a zero. For write operation, the station

will drive a one for the first bit time, and a zero for the second bit time. The 16 bits data field is then presented. The first bit

that is transmitted is bit 15 of the register content.

The INTR pin on the PHY will be asserted whenever one of 8 selectable interrupt events occur. Selection is made by setting

the appropriate bit in the upper half of the Interrupt Control / Status register. When the INTR bit goes active, the MAC

interface is required to read the Interrupt Control / Status register to determine which event caused the interrupt. The Status

bits are read only and clear on read. When INTR is not asserted, the pin is held in a high impedance state.

10BASE-T

When configured to run in 10BASE-T mode, either through hardware configuration, software configuration or ANeg, the PHY

will support all the features and parameters of the industry standards.

Parallel to Serial logic is used to convert the 2-bit data into the serial stream. The serialized data goes directly to the

Manchester encoder where it is synthesized through the output waveshaping driver. The waveshaper reduces any EMI

emission by filtering out the harmonics, therefore eliminating the need for an external filter.

The received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. This

eliminates the need for a 10BASE-T external filter. A Manchester decoder converts the incoming serial stream. Serial to

Parallel logic is used to generate the 2-bit data.

The received signal passes through a low-pass filter, which filters out the noise from the cable, board, and transformer. This

eliminates the need for a 10BASE-T external filter. A Manchester decoder converts the incoming serial stream. Serial to

Parallel logic is used to generate the 2-bit data.

100BASE-TX

When configured to run in 100BASE-TX mode, either through hardware configuration, software configuration or Aneg.