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AC104X-DS00-R 数据表(PDF) 11 Page - Broadcom Corporation.

部件名 AC104X-DS00-R
功能描述  2.5V 4-Port 10/100-TX Ethernet Transceiver
PDF  50 Pages
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制造商  BOARDCOM [Broadcom Corporation.]
网页  http://www.broadcom.com
标志 BOARDCOM - Broadcom Corporation.

AC104X-DS00-R 数据表(HTML) 11 Page - Broadcom Corporation.

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Preliminary Data Sheet
AC104X
12/11/01
B roa dcom Co rpo rat ion
Document
AC104X-DS00-405-R
Section 1: Functional Description
Page 3
TRANSMIT FUNCTION
In 100BASE-TX mode, the PHY transmit function converts synchronous 2-bit data to a pair of 125 Mbps differential serial
data streams. The serial data is transmitted over network twisted pair cables via an isolation transformer. Data conversion
includes 4B/5B encoding, scrambling, parallel to serial, NRZ to NRZI, and MLT-3 encoding. The entire operation is
synchronous to 25 MHz and 125 MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked
on to an external 25 MHz clock source.
The transmit data is transmitted from the MAC to the PHY via the TXD[1:0] signals. The 4B/5B encoder replaces the first
two nibbles of the preamble from the MAC frame with a /J/K/ code-group pair Start-of-Stream Delimiter (SSD), following the
onset of TX_EN signal. The 4B/5B encoder appends a /T/R/ code-group pair End-of-Stream Delimiter (ESD) to the end of
transmission in place of the first two IDLE code-groups that follow the negation of the TX_EN signal. The encapsulated data
stream is converted from 4-bit nibbles to 5-bit code-groups. During the inter-packet gap, when there is no data present, a
continuous stream of IDLE code-groups are transmitted. When TX_ER is asserted while TX_EN is active, the Transmit Error
code-group /H/ is substituted for the translated 5B code word. The 4B/5B encoding is bypassed when Reg. 21.1 is set to “1”,
or the PCSBP pin is strapped high.
In 100BASE-TX mode, the 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher function in
order to reduce radiated emissions on the twisted pair cable. The scrambler encodes a plain text NRZ bit stream using a key
stream periodic sequence of 2047 bits generated by the recursive linear function:
X[n] = X[n-11] + X[n-9] (modulo 2)
The scrambler reduces peak emissions by randomly spreading the signal energy over the transmitted frequency range, thus
eliminating peaks at any single frequency. For repeater applications, where all ports transmit the same data simultaneously,
signal energy is spread further by using a non-repeating sequence for each PHY, i.e., the scrambled seed is unique for each
different PHY based on the PHY address.
PARALLEL TO SERIAL, NRZ TO NRZI, AND MLT3 CONVERSION
The 5-bit NRZ data is clocked into PHY's shift register with a 25 MHz clock, and clocked out with a 125 MHz clock to convert
it into a serial bit stream. The serial data is converted from NRZ to NRZI format, which produces a transition on Logic 1 and
no transition on Logic 0. To further reduce EMI emissions, the NRZI data is converted to an MLT-3 signal. The conversion
offers a 3dB to 6dB reduction in EMI emissions. This allows system designers to meet the FCC Class B limit. Whenever
there is a transition occurring in NRZI data, there is a corresponding transition occurring in the MLT-3 data. For NRZI data,
it changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction
after every two transitions. The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock
information. The conversion requires detecting the transitions of the incoming NRZI data and setting the count up/down
direction for the MLT-3 data.
The slew rate of the transmitted MLT-3 signal can be controlled to reduce EMI emissions. The MLT-3 signal after the
magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the ANSI TP- PMD
standard. This is guaranteed with either 1:1 or 1.25:1 transformer.
RECEIVE FUNCTION
The 100BASE-TX receive path functions as the inverse of the transmit path. The receive path includes a receiver with
adaptive equalization and DC restoration in the front end. It also includes a MLT-3 to NRZI converter, 125 MHz data and
clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, and 5B/4B decoder. The receiver circuit
starts with a DC bias for the differential RX+/- inputs, followed with a low-pass filter to filter out high frequency noise from the
transmission channel media. An energy detect circuit is also added to determine whether there is any signal energy on the
media. This is useful in the power-saving mode. The amplification ratio and slicer's threshold is set by the on-chip bandgap
reference.



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