DAC5686IPZP datasheet(38/46 Pages) TI

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fullscale

16 V

extio

biasj

(GAINCODE ) 1)

B 1 *

FINEGAIN

3072

DIGITAL INPUTS

DA[15:0]

DB[15:0]

SLEEP

PHSTR

TxENABLE

QFLAG

SDIO

SCLK

SDENB

Internal

Digital In

IOVDD

IOGND

RESETB

Internal

Digital In

IOVDD

IOGND

CLOCK INPUT AND TIMING

CLK

Internal

Digital In

CLKC

CLKGND

10 k

Ω

CLKVDD

10 k

Ω

10 k

Ω

10 k

Ω

CLKVDD

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

dacb_offset[10:8]: The upper 3 bits of the DACA _offset

sleepb: When asserted, DACB is put into the sleep mode.

dacb_gain[11:8]: Coarse gain control for DACB; the full-scale output current is:

where GAINCODE is the decimal equivalent of dacb_gain [11:8] {0

…15} and the FINEGAIN is dacb_gain [1:0] as

2s complement [–127

…128].

Figure 42 shows a schematic of the equivalent CMOS digital inputs of the DAC5686. DA[0:15], DB[0:15], SLEEP,

PHSTR, TxENABLE, QFLAG, SDIO, SCLK, and SDENB have pulldown resistors and RESETB has a pullup

resistor internal to the DAC5686. See the specification table for logic thresholds.

Figure 42. CMOS/TTL Digital Equivalent Input

Figure 43 shows an equivalent circuit for the clock input.

Figure 43. Clock Input Equivalent Circuit

DAC5686IPZP 数据表(PDF) 38 Page - Texas Instruments

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