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PHSTR

D[0:15]

PLLLOCK

DAC1

CLK2

CLK2C

T0004-01

Digital Filters

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

Figure 35. Using PHSTR to Synchronize PLLLOCK Input Clock for Multiple DACs in External Clock Mode

equal to 50% of the DAC output sample clock period up to a maximum of 1 ns. At 500 MHz, the setup and hold

times are therefore 0.5 ns. The PHSTR signal can remain high after synchronization, or can return low. A new

low-to-high transition resynchronizes the input clock. Note that the PHSTR transition also resets the NCO

accumulator.

Figure 36 through Figure 39 show magnitude spectrum responses for 2

×, 4×, 8×, and 16× FIR interpolation

attenuation for all four configurations. The filters are linear phase. The sel field in register config_lsb selects the

interpolation filtering rate as 2

×, 4×, 8×, or 16×; interpolation filtering can be completely bypassed by setting

fullbypass in register config_lsb.

Figure 40 shows the spectral correction of the DAC sinx/x rolloff achieved with use of inverse sinc filtering.

config_msb.

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