DAC5686IPZP datasheet(5/46 Pages) TI

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DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

DEVICE INFORMATION (continued)

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

BIASJ

I/O

Full-scale output current bias

CLK1

External clock input; data clock input

CLK1C

Complementary external clock input; data clock input

CLK2

External clock input; sample clock for the DAC (optional if PLL disabled)

CLK2C

Complementary external clock input; sample clock for the DAC (optional if PLL disabled)

CLKGND

58, 64

Ground return for internal clock buffer

CLKVDD

Internal clock buffer supply voltage

DA[15:0]

34–36,

A-channel data bits 0 through 15

39–43,

DA15 is most significant data bit (MSB).

48–55

DA0 is least significant data bit (LSB).

DB[0:15]

71–78,

B-channel data bits 0 through 15

83–87,

DB15 is most significant data bit (MSB).

90–92

DB0 is least significant data bit (LSB).

Note: The order of the B data bus can be reversed by register rev_bbus.

DGND

27, 38, 45,

Digital ground return

57, 69, 81,

88, 93, 99

DVDD

26, 32, 37,

Digital supply voltage

44, 56, 68,

82, 89, 100

EXTIO

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).

Used as internal reference output when EXTLO = AGND, requires a 0.1-

µF decoupling capacitor to

AGND when used as reference output

EXTLO

Internal reference ground. Connect to AVDD to disable the internal reference

IOUTA1

A-channel DAC current output. Full scale when all input bits are set to 1

IOUTA2

A-channel DAC complementary current output. Full scale when all input bits are set to 0

IOUTB1

B-channel DAC current output. Full scale when all input bits are set to 1

IOUTB2

B-channel DAC complementary current output. Full scale when all input bits are set to 0

IOGND

47, 79

Digital I/O ground return

IOVDD

46, 80

Digital I/O supply voltage

LPF

I/O

PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V).

PHSTR

The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets

the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition

sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO

phase accumulator.

PLLGND

Ground return for internal PLL

PLLVDD

PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.

PLLLOCK

PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In

external clock mode, PLLLOCK outputs the input rate clock.

QFLAG

Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an

output to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can

be left open when not used.

RESETB

Resets the chip when low

SCLK

Serial interface clock

SDENB

Active-low serial data enable, always an input to the DAC5686

SDIO

I/O

Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin

serial interface mode.

SDO

High-impedance state (the pin is not used) in the three-pin serial interface mode. Serial-port output data

in the four-pin serial interface mode.

SLEEP

Asynchronous hardware power-down input. Active high. Internal pulldown

TESTMODE

TESTMODE is DGND for the user.

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