DAC5686IPZP datasheet(39/46 Pages) TI

部件名	DAC5686IPZP

功能描述	16-BIT, 500-MSPS, 2X16X INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER

PDF	46 Pages

Scroll/Zoom	100%

制造商	TI [Texas Instruments]

网页	http://www.ti.com

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200

Ω

CLK

1:4

CLKC

Termination Resistor

Swing Limitation

Optional, May Be Bypassed

for Sine Wave Input

CAC

0.1

µF

Ropt

Ω

CLK

1:1

CLKC

Optional, Reduces

Clock Feed-Through

CAC

0.01

µF

TTL/CMOS

Source

Ropt

Ω

CLK

CLKC

Node CLKC Internally Biased

to CLKVDD 2

TTL/CMOS

Source

0.01

µF

130

Ω

CAC

0.1

µF

CAC

0.1

µF

130

Ω

VTT

Differential

ECL

(LV)PECL

Source

–

CLK

CLKC

82.5

Ω

82.5

Ω

100

Ω

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

Figure 44, Figure 45, and Figure 46 show various input configurations for driving the differential clock input

(CLK/CLKC).

Figure 44. Preferred Clock Input Configuration

Figure 45. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source

Figure 46. Driving the DAC5686 With a Differential ECL/PECL Clock Source

DAC5686IPZP 数据表(PDF) 39 Page - Texas Instruments

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