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Clock Generation

t

_align

+

1

2F

CLK2

* 0.5 ns

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

In the DAC5686, the internal clocks (1

×, 2×, 4×, 8×, and 16×, as needed) for the logic, FIR interpolation filters,

and DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or the

DAC output sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) is

separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing phase noise

within the PLL.

The DAC5686 has three clock modes for generating the internal clocks (1

×, 2×, 4×, 8×, and 16×, as needed) for

the logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in

register config_usb. A block diagram for the clock generation circuit is shown in Figure 27.

1. PLLVDD = 0V and dual_clk = 0: EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through

CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used, so the LPF circuit is not applicable. The input

data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the

PLLLOCK pin. It is common to use the PLLLOCK clock to drive the chip that sends the data to the DAC;

otherwise, there is phase ambiguity regarding how the DAC divides down to the input sample rate clock and

an external clock divider divides down. (For a divide by N, there are N possible phases.) The phase

ambiguity can also be solved by using PHSTR pin with a synchronization signal.

2. PLLVDD = 3.3V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE

Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock

generation blocks (CLKVDD and CLKGND), thus minimizing PLL phase noise.

In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through

CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC

generates the higher speed DAC sample rate clock using an internal PLL/VCO. In PLL clock mode, the user

provides a differential external reference clock on CLK1/CLK1C.

A type-4 phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback

clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is

generated by dividing the VCO output by 1

×, 2×, 4×, or 8× as selected by the prescaler (div[1:0]). The output

of the prescaler is the DAC sample rate clock and is divided down to generate clocks at

÷2, ÷4, ÷8, and ÷16.

The feedback clock is selected by the registers sel[1:0], an then is fed back to the PFD for synchronization

to the input clock. The feedback clock is also used for the data input rate, so the ratio of DAC output clock to

feedback clock sets the interpolation rate of the DAC5686. The PLLLOCK pin is an output that indicates

when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user at pin LPF. See

the low-pass filter section for filter setting calculations. This is the only mode where the LPF filter applies.

3. PLLVDD = 0V and dual_clk = 1: DUAL CLOCK MODE

In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and at the input

data rate through CLK1/CLK1C. The DUAL CLOCK MODE has the advantage of a clean external clock for

the DAC sampling without the phase ambiguity. The edges of CLK1 and CLK2 must be aligned to within

±t

where F

F

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