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DA[15:0]

QFLAG

CLK1 or

PLLLOCK

T0001-01

Clock Synchronization Using the PHSTR Pin in External Clock Mode

CLK2

PLLLOCK

CLK2C

T0003-01

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

Figure 33. Interleave Bus Mode Timing Diagram Using QFLAG

The dual-clock mode is selected by setting dualclk high in the config_usb register. In this mode, the DAC5686

uses both clock inputs; CLK1/CLK1C is the input data clock, and CLK2/CLK2C is the external clock. The edges

of the two input clocks must be phase-aligned within

±500 ps to function properly.

In external clock mode, the DAC5686 is clocked at the DAC output sample frequency (CLK2 and CLK2C). For an

interpolation rate N, there are N possible phases for the DAC input clock on the PLLLOCK pin (see Figure 34 for

N = 4).

Figure 34. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode

To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a sync signal on the PHSTR pin is used.

During configuration of the DAC5686 chips, address sync_phstr in config_msb is set high to enable the

PHSTR input pin as a sync input to the clock dividers generating the input clock. A simultaneous low-to-high

transition on the PHSTR pin for each DAC5686 then forces the input clock on PLLLOCK to start in phase on

each DAC. See Figure 35.

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