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DAC5686 EVALUATION BOARD

Appendix A. PLL LOOP FILTER COMPONENTS

R3

C3

R1

C1

C2

External

Internal

S0006-01

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows

the user the flexibility to operate the DAC5686 in various configurations. Possible output configurations include

transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. The digital

inputs are designed to be driven directly from various pattern generators with the onboard option to add a

resistor network for proper load termination.

For the external second-order filter shown in Figure 50, the components R, C1, and C2 are calculated for a

desired phase margin and loop bandwidth. Resistor R3 = 200

Ω and capacitor C3 = 8 pF are internal to the

DAC5686.

Figure 50. DAC5686 Loop Filter

The VCO gain (Gvco) as a function of VCO frequency for the DAC5686 is shown in Figure 17. For a desired

VCO

frequency,

the

loop

filter

values

can

be

calculated

using

the

following

equations.

Nominal PLL design parameters include:

Charge pump current:

iqp = 1 mA

VCO gain:

PLL divide ratio

× interpolation:

N = {2, 4, 8, 16, 32}

Phase detector gain:

Let

Desired loop bandwidth =

ω

d

Desired phase margin =

φ

d

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