MAS6505 datasheet(30/44 Pages) MAS

30 / 44 page

DA6505.005

11 June 2018

30 (44)

SERIAL DATA INTERFACE CONTROL

Serial Interface

MAS6505 is operated via serial bus communication.

The

MAS6505

acts

slave

device

and

communication is initiated only by an external master

device that is connected to the serial bus.

The MAS6505 supports 2-wire serial I2C bus and 4-

and 3-wire serial SPI bus. Selection between I2C

and SPI communication is done by CSB chip select

pin. The CSB=high selects I2C and CSB=low

activates SPI communication. In I2C communication

the CSB pin can be either connected to VDDIO or

left unconnected (floating) since the CSB pin has

internal 250 kΩ pull-up resistor to VDDIO. The 2-wire

serial I2C bus type interface comprises of serial

clock input (SCK) and bi-directional serial data (SDI)

input/output.

The

I2C

bus

used

write

configuration data to sensor interface IC and read

the measurement result when measurement has

been finished. The interface is also used for reading

the calibration data from the non-volatile EEPROM

memory.

Note: The 2-wire I2C bus of MAS6505 supports only

basic I2C bus communication protocol but not for

example 10-bit addressing, arbitration and clock

stretching features of the I2C bus specification.

The alternative 4-wire serial SPI bus type interface

comprises of serial clock input (SCK), serial data

input (SDI), serial data output (SDO) and chip select

input (CSB). In the 3-wire mode the SDI pin operates

as both data input and data output. The SPI bus wire

selection is done by WIRE bit in the Configuration

4-wire mode (WIRE=0). The 3-wire mode can be

selected by setting WIRE=1.

The serial bus has an additional SPI mode lock in

feature. By pulling CSB low and giving at least four

SCK clock pulses makes the digital interface to lock

into SPI communication mode. This is done in order

to avoid inadvertently decoding SPI traffic to another

slave device as I2C data. After entering SPI lock

mode the I2C communication is possible only after

applying power on reset.

MAS6505 has Reset register (EC/6CHEX) which

allows resetting the device via serial interface.

Writing any data byte to the Reset register

(EC/6CHEX). Reset initializes counters and the serial

communication bus and resets all registers from

FF/7FHEX to EC/6CHEX to a default zero (00HEX) value.

Reading from the reset register is not possible.

I2C Bus Communication

The

I2C

bus

communication

selected

connecting the CSB pin to VDDIO or leaving it

unconnected (floating).

The I2C bus standard makes it possible to connect

several different devices on same bus. The devices

are distinguished from each other by unique device

addresses. The MAS6505 device address is shown

in the following Table 12Table . The LSB bit of the

device address (using 8-bit address notation)

defines whether the bus is configured to Read (1) or

Write (0) operation. See Figures 4 and 15 showing

MAS6505 configured for I2C bus communication.

Table 12. MAS6505 I2C bus hard wired device address (EA/EBHEX for Write/Read)

W/R

0/1

I2C Bus Protocol Definitions

Data transfer is initiated by master with a Start bit (S)

when SDI is pulled low while SCK stays high. Then,

SDI sets the transferred bit while SCK is low and the

data is sampled (received) when SCK rises. When

the transfer is complete, a Stop bit (P) is sent by

releasing the data line to allow it to be pulled up while

SCK is constantly high.

Figure 7 on next page shows the start (S) and stop

(P) bits and a data bit. Data must be held stable at

the SDI pin when SCK is high. Data at the SDI pin

can change value only when SCK is low.

Each SDI line byte transfer must contain 8-bits

where the most significant bit (MSB) always comes

first.

Each

byte

has

followed

acknowledge bit (see further below). The number of

bytes transmitted per transfer is unrestricted.

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