ADMV4420ACPZ-R2 datasheet(37/61 Pages) AD

37 / 61 page

Data Sheet

ADMV4420

Rev. A | Page 37 of 61

THEORY OF OPERATION

REFERENCE INPUT STAGE

The reference input stage is shown in Figure 121 and employs a

differentially excited, 50 MHz crystal oscillator. Alternatively,

the reference input can be driven by an external singled-ended

50 MHz source. Use the REF_IN_MODE bit (Register 0x20E,

Bit 1) to select the input configuration. To select crystal

oscillator mode, set this bit to 0 to close the SW1 switch and

open the SW2 switch. To select single-ended mode, set this bit

to 1 to close the SW2 switch and open the SW1 switch.

The selection of a crystal oscillator must be such that the

electrical series resistance (ESR) and the load capacitance are

well defined. For worst case demonstration purposes, the

crystal oscillator selected for the evaluation board uses a

maximum ESR of 100 Ω. To ensure the crystal oscillation

startup over all temperature and process variations, a maximum

ESR of 40 Ω is recommended. The nominal crystal load

capacitance (CLOAD) = 10 pF, which is computed from series

combination of the C5 and C6 capacitors. It is recommended to

keep CLOAD between 8 pF and 12 pF. Additionally, ensure that

C21 is not installed for crystal oscillator mode, as this can

impact capacitive loading on the crystal, which can in turn

prevent the oscillation from starting up.

REFERENCE DOUBLER, R COUNTER, AND RDIV2

Following the reference input stage as shown in Figure 121,

there is an internal reference multiply by 2 block (×2 doubler)

that allows generation of higher phase frequency detector

frequencies (fPFD). A higher fPFD is useful for improving overall

system phase noise performance. Typically, doubling the fPFD

improves the inband phase noise performance by up to

3 dBc/Hz. Use the EN_REF_X2 bit (Register 0x20E, Bit 2) to

enable the reference doubler, which toggles the SW3 switch, as

shown in Figure 121.

Following the reference doubler block, there are two frequency

dividers: a 10-bit R counter (1 to 1023 allowed) and a divide

by 2 block. These dividers allow the input reference frequency

(fREF) to be divided down to produce lower fPFD, which helps to

minimize fractional-N integer boundary spurs at the output.

The R counter is set using the R_DIV bits in Register 0x20C

and Register 0x20D. If the R_DIV = 1, the SW4 switch is in the

position shown in Figure 121. Otherwise, the SW4 switch

toggles to use the R counter.

The reference divide by 2 block is enabled by using the RDIV2_

SEL bit (Register 0x20E, Bit 0), which toggles the SW5 switch,

as shown in Figure 121.

×2

DOUBLER

SW3

10-BIT

R COUNTER

SW4

÷2

SW5

PFD

SW1

SW2

C21

XTAL2/NC

REF/XTAL1

EXTERNAL

REFERENCE

Figure 121. Reference Input Path Block Diagram

ADMV4420ACPZ-R2 数据表(PDF) 37 Page - Analog Devices

ADMV4420ACPZ-R2 数据表(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

数据表下载