ADMV4420ACPZ-R2 datasheet(50/61 Pages) AD

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ADMV4420

Data Sheet

Rev. A | Page 50 of 61

ADDRESS 0x213, RESET: 0x01, NAME: PLL_MUX_SEL

PLL Mux Select

00001000: Output Logic High.

00000101:

VCO/(2 x N)

NDiv-by-2 to Mux Out, Frequency =

00000100:

REFIN/(2 x R)

RDiv-by-2 to Mux Out, Frequency =

00000001: Digital Lock Detect.

00000000: Output Logic Low.

[7:0] PLL_MUX_SEL (R/W)

Table 31. PLL_MUX_SEL Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[7:0]

PLL_MUX_SEL

PLL mux select bits

0x1

R/W

00000000: Output logic low

00000001: Digital lock detect

00000100: R divide by 2 to mux out, frequency = REFIN /2 × R)

00000101: N divide by 2 to mux out, frequency = VCO/(2 × N)

00001000: Output logic high

ADDRESS 0x214, RESET: 0x98, NAME: LOCK_DETECT

Lock Detect Bias

11: 10uA.

10: 20uA.

01: 30uA.

00: 40uA.

Lock Detect Count

011:

Declare Lock.

8192 Consecutive PFD Cycles to

010:

Declare Lock.

4096 Consecutive PFD Cycles to

001:

Declare Lock.

2048 Consecutive PFD Cycles to

000:

Declare Lock.

1024 Consecutive PFD Cycles to

[7:6] LD_BIAS (R/W)

[2:0] RESERVED

[5:3] LD_COUNT (R/W)

Table 32. LOCK_DETECT Bit Descriptions

Bits

Bit Name

Description

Reset

Access

[7:6]

LD_BIAS

Lock detect bias bits

0x2

R/W

00: 40 μA

01: 30 μA

10: 20 μA

11: 10 μA

[5:3]

LD_COUNT

Lock detect count bits

0x3

R/W

000: 1024 consecutive PFD cycles to declare lock

001: 2048 consecutive PFD cycles to declare lock

010: 4096 consecutive PFD cycles to declare lock

011: 8192 consecutive PFD cycles to declare lock

[2:0]

RESERVED

Reserved

0x0

R/W

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