ADMV4420ACPZ-R2 datasheet(8/61 Pages) AD

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ADMV4420

Data Sheet

Rev. A | Page 8 of 61

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GND.

24 SDO

23 GND

22 CPOUT

21 VPOS3_CP

20 ENBL1

19 ENBL0

18 GND

17 GND

GND

RFIN

GND

DECL1_VCO1

DECL2_VCO2

PIN 1

INDICATOR

ADMV4420

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3, 5, 6,

16, 17, 18,

23, 31

GND

Ground. Connect these pins and package bottom to RF and dc ground. See Figure 4 for the GND interface

schematic.

RFIN

RF Input Pin. This pin has a 50 Ω input impedance.

7, 8

DECL1_VCO1,

DECL2_VCO2

LDO Regulator Decoupling Pin. Place a 10 µF capacitor close to this pin.

VPOS1_VCO

5 V Power Supply Pin. Place 0.1 µF and 100 pF decoupling capacitors close to this pin.

10, 11, 32

DECL3_PLL,

DECL4_SDM,

DECL5_RF

LDO Decoupling Pin. Place a 10 µF capacitor close to this pin.

VPOS2_PLL

5 V Power Supply. Place the 0.1 µF and 100 pF decoupling capacitor close to this pin.

XTAL2/NC

Crystal Input or No Connect. When using an external crystal, place the crystal between the REF/XTAL1 and

XTAL2/DNC pins. When an external reference input signal is applied through the REF/XTAL1 pin, this pin is

used as a No Connect pin. Connect this pin to ground with a 1 nF capacitor (ac ground) when an external

reference input signal is applied through the REF/XTAL1 pin.

REF/XTAL1

External Reference Input or Crystal Input. When using an external crystal, place the crystal between the

XTAL1 and XTAL2 pins. When using as external reference input, apply an external reference signal to this

pin with a 0.01 µF, dc blocking capacitor. Refer to Figure 121 for the external reference input configuration.

This pin is internally biased to 1.65 V.

MUXOUT

PLL Multiplexer Output.

ENBL0

Device Enable 0. For nominal operation, keep this pin tied to 3.3 V.

ENBL1

Device Enable 1. For nominal operation, keep this pin tied to 3.3 V

VPOS3_CP

5 V Power Supply. Place the 0.1 µF and 100 pF decoupling capacitor close to this pin.

CPOUT

Synthesizer Charge Pump Output. Connect this pin to VTUNE (Pin 28) through the loop filter

SDO

Serial Peripheral Interface (SPI) Data Output. 3.3 V logic.

SDI

SPI Data Input. 3.3 V logic.

SCLK

SPI Clock. 3.3 V logic.

SPI Chip Select. 3.3 V logic. Active low.

VTUNE

VCO Tuning Voltage. This pin is driven by the output of the loop filter.

VPOS4_IF

5 V Power Supply. Place 0.1 µF and 100 pF decoupling capacitors close to this pin.

IFOUT

IF Output. This pin has a 75 Ω output impedance. The output stage of the IF amplifier is an open-collector

configuration and requires a dc bias of 5 V. Use a bias choke inductor. See the IF Output—External

Inductor/Biasing section for more details.

EPAD

Exposed Pad. The exposed pad must be connected to GND.

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