ADMV4420ACPZ-R2 datasheet(38/61 Pages) AD

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ADMV4420

Data Sheet

Rev. A | Page 38 of 61

N COUNTER

The N counter allows a division ratio in the PLL feedback path

from the VCO. Note that the VCO signal is multiplied by 2 to

achieve the LO frequency at the double balanced mixer. The

division ratio is determined using the integer-N (INT),

fractional-N (FRAC), and modulus (MOD) values that this

counter comprises. The applicable registers for setting the INT,

FRAC, and MOD values are Register 0x200 to Register 0x20A.

FRAC

VALUE

MOD

VALUE

INT

VALUE

N = INT + FRAC/MOD

TO PFD

N COUNTER

FROM VCO

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

Figure 122. N Counter Functional Diagram

INT, FRAC, MOD, AND REFERENCE PATH

RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the

reference path, make it possible to generate VCO frequencies

spaced by fractions of the fPFD.

The fPFD can be calculated from the reference frequency (fREF)

and the reference path configuration parameters,

)

PFD

REF

×+

(1)

where:

D is the reference doubler bit (0 or 1).

R is the reference divide ratio of the binary, 10-bit

programmable counter (1 to 1023).

T is the reference divide by 2 bit (0 or 1).

The VCO frequency (fVCO) is calculated with the following

equation:

VCO

PFD

(2)

where:

fLO is the frequency of the LO driving the mixer.

N is the desired value of the N counter.

The N counter value is defined as:

VCO

PFD

FRAC

N INT

MOD

(3)

where:

INT is the 16-bit integer value (75 to 65,535).

FRAC is the numerator of the 24-bit primary modulus value

(0 to 16,777,215).

MOD is the denominator of the 24-bit primary modulus value

(1 to 16,777,215).

To obtain the INT portion of the N counter value, round down

using the mathematical floor function,

INT = FLOOR(N)

(4)

where FLOOR is the mathematical floor function.

To determine the value of the MOD parameter, a channel

spacing step size (fCHSP) and the fPFD must be selected first.

The MOD parameter is then computed with the fPFD and the

greatest common denominator (GCD),

(

PFD

CHSP

PFD

MOD

GCD f

(5)

The FRAC value can be computed for a given an N counter

value, INT value, and MOD value,

FRAC = FLOOR(MOD × (N –INT))

(6)

INTEGER-N MODE

When the FRAC value is equal to zero, the synthesizer operates

in integer-N mode.

PHASE FREQUENCY DETECTOR AND CHARGE

PUMP

The PFD takes inputs from the R counter and N counter to

produce an output that is proportional to the phase and

frequency differences between them. This proportional

information is then output to a charge pump (CP) circuit that

generates current to drive an external loop filter, which is then

used to appropriately increase or decrease the VTUNE tuning

voltage.

Figure 123 shows a simplified schematic of the PFD and CP.

Note that the PFD includes a fixed delay element, which is used

to ensure there is no dead zone in the PFD transfer function for

consistent reference spur levels.

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