ADMV4420ACPZ-R2 datasheet(40/61 Pages) AD

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ADMV4420

Data Sheet

Rev. A | Page 40 of 61

MUX

MUXOUT

OUTPUT LOW

DIGITAL LOCK DETECT

R COUNTER/2

N COUNTER/2

OUTPUT HIGH

Figure 125. Multiplexer Output Diagram

DIGITAL LOCK DETECT

The digital lock detect function that is output on the MUXOUT

pin has two adjustable settings in Register 0x214. LD_BIAS

adjusts an internal precision window and LD_COUNT adjusts

the consecutive cycle count to declare PLL lock. It is recom-

mended to keep the 20 µA and 8192 PFD cycle count factory

settings. For special applications, contact Analog Devices

technical support for guidance on adjusting these settings.

ENABLES

80 mW of power dissipation. For nominal operation, keep all

enables in this register set to 1 (register value of 0x6F). Note that

Bit 4 and Bit 7 are reserved and must be set to 0.

IF OUTPUT—EXTERNAL INDUCTOR/BIASING

The IF amplifier output is an open-collector configuration and

requires an external biasing inductor pulled up to the

VPOS4_IF supply. The recommended value of the inductor is

approximately 50 nH, which requires a current carrying

capability of at least 150 mA. Because this configuration is

dc-coupled, it is necessary to place a series capacitor between

the IF output and the next stage in the end application. A

recommended minimum value for the series capacitor is 1 nF.

SPI CONFIGURATION

The SPI of the ADMV4420 allows configuration of the device

for specific functions or operations via the 4-pin SPI port. This

interface provides users with added flexibility and customization.

The SPI consists of four control lines: SCLK, SDI, SDO, and CS.

The ADMV4420 protocol consists of a write/read bit followed

by 15 register address bits and 8 data bits. The address field and

data field are organized MSB first and end with the LSB.

For a write operation, set the MSB to 0, and for a read

operation, set the MSB to 1. The write cycle sampling must be

done on the rising edge of SCLK. The 24 bits of the serial write

address and data are shifted in on the SDI control line, MSB to

LSB. The ADMV4420 input logic level for the write cycle

supports a 3.3 V interface.

For a read cycle, the R/W bit and the 15 bits of address shift in

on the rising edge of SCLK on the SDI control line. Then, 8 bits

of serial read data shift out on the SDO control line, MSB first,

on the falling edge of SCLK. The output logic level for a read

cycle is 3.3 V. The output drivers of the SDO are enabled after

the last rising edge of SCLK of the instruction cycle and remain

active until the end of the read cycle. In a read operation, when

CS is deasserted, SDO returns to high impedance until the next

read transaction. The CS is active low and must be deasserted at

the end of the write or read sequence.

An active low input on CS starts and gates a communication

cycle. The CS pin allows more than one device to be used on the

same serial communications lines. The SDO pin goes to a high

impedance state when the CS input is high. During the

communication cycle, the chip select must stay low.

The SPI communications protocol follows the Analog Devices

SPI standard. For more information, see the ADI-SPI Serial

Control Interface Standard (Rev 1.0).

VCO AUTOCALIBRATION AND AUTOMATIC LEVEL

CONTROL

The multicore VCO uses an internal autocalibration

(AUTOCAL) and automatic level control (ALC) routine that

optimizes the VCO settings for a particular frequency and

allows the PLL to lock in approximately 400 µs after the lower

portion of the N counter integer value (INT_L) has been

programmed. For nominal applications, maintain the

AUTOCAL and ALC default values in the register map (see

Table 8).

PROGRAMMING SEQUENCE

A number of double buffered registers that take effect only after

a write to the lower portion of the N counter integer value

(INT_L). The INT_L register applies any changes to these

double registers and initiate the autocalibration routine.

Additionally, it is recommended to allow 16 SPI clock cycles

after writing to the INT_L register.

The following describes the recommended programming

sequence:

1. Program the CP_CURRENT register (Register 0x22E).

2. Program the FRAC_H register (Register 0x204).

3. Program the FRAC_M register (Register 0x203).

4. Program the FRAC_L register (Register 0x202).

5. Program the MOD_H register (Register 0x20A).

6. Program the MOD_M register (Register 0x209).

7. Program the MOD_L register (Register 0x208).

8. Program the INT_H register (Register 0x201).

9. Program the INT_L register (Register 0x200).

10. Program 16 SPI clock cycles.

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