ADMV4420ACPZ-R2 datasheet(57/61 Pages) AD

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Data Sheet

ADMV4420

Rev. A | Page 57 of 61

Figure 130. ADMV4420-EVALZ Evaluation Board, Layer 4 (Bottom Side)

Figure 126 shows the ADMV4420-EVALZ evaluation board

with component placement. The decoupling capacitors on the

LDO decoupling pin and power supply traces to minimize noise

effects. The schematic and Pb-free reflow solder profile of the

evaluation board are shown in and Figure 2 and Figure 132,

respectively.

There are two options to power up the evaluation board. The

first option is to apply a 5 V supply to the VPOS1, VPOS2,

VPOS3, and VPOS4 test points for the VCO, PLL, CP, and IF

blocks (VPOS1_VCO, VPOS2_PLL, VPOS3_CP, and

VPOS4_IF pins) respectively, and connect a 0 V supply to one

of the GND1, GND2, or GND3 ground test points. In this

option, remove the R13, R14, R15, and R16 resistors from the

evaluation board. This option allows the user to monitor the

currents of each block separately.

The second option to power up the board requires the power

supply to be applied through the VCC5P0 test point with the

appropriate ground connection. Only the total current of the

ADMV4420 can be monitored with this option. After powering

up the evaluation board, program the required digital settings

for the target configuration through the SDP-S controller board

by using the Analysis, Control, Evaluation (ACE) software,

which can be downloaded from the Analysis, Control,

Evaluation (ACE) product page. See the ADMV4420-EVALZ

user guide for details.

There are two different options to apply an external reference

input to the ADMV4420, as shown in Figure 132. The required

configurations for these options are described in Table 46.

When using the Case 1 option, the external reference input is

applied through the J2 connector with a signal generator. When

using the Case 2 option, the external reference input is provided

by the crystal (Y1).

A loop filter circuit generates the VCO control voltage (VTUNE)

by applying the CP current output of the ADMV4420 from the

charge pump output pin (CPOUT) to obtain the target LO

frequency. Figure 131 shows the recommended schematic and

Table 47 describes the loop filter components when the phase

frequency detector frequency is 50 MHz. Table 48 describes the

complete list of materials, which includes the loop filter

components. For details about the evaluation board, see the

ADMV4420-EVALZ user guide.

Table 46. External Reference Input Configurations

Option

Component Configuration

Case 1

Populate C21. Replace C6 with 1 nF capacitor.

Remove C5 and Y1.

Case 2 (Default)

C5 = 20 pF, C6 = 20 pF. Do not populate C21.

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