ADMV4420ACPZ-R2 datasheet(55/61 Pages) AD

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Data Sheet

ADMV4420

Rev. A | Page 55 of 61

APPLICATIONS INFORMATION

EVALUATION BOARD

The ADMV4420-EVALZ evaluation board can be used to

evaluate the performance of the ADMV4420. The top and cross

sectional layout views of the ADMV4420-EVALZ evaluation

board are shown in Figure 126 and Figure 127, respectively. The

RF transmission lines were designed using a coplanar waveguide

(CPWG) model with a line width (W) of 16 mil and 13 mil of

ground spacing for a characteristic impedance of 50Ω for the

RF input (RFIN) and the external reference input (REF/XTAL1).

The line width and ground spacing for the IF output (IFOUT)

are 9 mil and 15 mil, respectively. The PCB is made with Rogers

4350B dielectric material, which offers low loss performance,

and isola 370HR dielectric material, which achieves the

required thickness of the PCB.

The ADMV4420-EVALZ evaluation board layout consists of

four layers. Layer 1 contains the charge pump, IF supplies

(VPOS3_CP and VPOS4_IF), and the multiplexer output signal

(MUXOUT) trace, which are routed together with the

peripheral component placements. Layer 2 is arranged to

provide the ground plane for the board. Layer 3 includes the

VCO (VPOS1_VCO) supply, the PLL (VPOS2_PLL) supply,

and digital SPI control signal (CS, SDI, SDO, and SCLK) traces,

and Layer 4 includes the chip enable (ENBL0 and ENBL1) traces

on the bottom side of the board. Note that on the evaluation

board, CS is indicated by CSB. Figure 128 to Figure 130 show

the routing details of Layer 2 to Layer 4. For optimal RF and

thermal grounding place as many plated through vias as possible

around the RF transmission lines, underneath the exposed pad

and throughout the entire PCB (See Figure 128).

Figure 126. ADMV4420-EVALZ Evaluation Board Layout, Top View (Layer 1)

ADMV4420ACPZ-R2 数据表(PDF) 55 Page - Analog Devices