ADE7763ARS datasheet(45/56 Pages) AD

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ADE7763

Rev. A | Page 45 of 56

ade up of four signals:

The serial interface of the ADE7763 is m

SCLK, DIN, DOUT, and CS. The serial clock for a data transfer

is applied at the SCLK logic input. This logic input has a Schmitt-

trigger input structure that allows slow rising and falling clo

edges to be used. All data transfer operations are synchronized

to the serial clock. Data is shifted into the ADE7763 at the DIN

logic input upon the falling edge of SCLK. Data is shifted out o

the ADE7763 at the DOUT logic output upon a rising edge o

SCLK. The

CS logic input is the chip-select input. This input is

used when multiple devices share the serial bus. A falling edge

upon CS also resets the serial in

into communication mode. T

terface and places the ADE7763

he CS input should be driven low

for the entire data transfer operation. Bringing CS high during a

data transfer operation aborts the transfer and places the serial

bus in a high impedance state. The CS logic input can be tied

low if the ADE7763 is the only device on the serial bus. However,

with CS tied low, all initiated data transfer operations must be

fully completed, i.e., the LSB of each register must be transferred

because there is no other way to bring the ADE7763 into commu-

nication mode without resetting the entire device using RESET.

ADE7763 Serial Write Operation

The serial write sequence takes place as follows. With the

ADE7763 in communication mode (i.e., the CS input logic low),

first a write to the communication register occurs. The MSB of

this byte transfer is a 1, indicating that the data transfer

operation is a write. The LSBs of this byte contain the address of

the register to be written to. The ADE7763 starts shifting in the

bits of register data are shifted in upon the falling edge of

subsequent SCLK pulses—see Figure 83. As explained earlier,

the data write is initiated by a write to the communication

data is transferred to all on-chip registers one byte at a time.

After a byte is transferred into the serial port, there is a finite

time before it is transferred to one of the ADE7763 on-chip

registers. Although another byte transfer to the serial port can

start while the previous byte is being transferred to an on-chip

4 µs after the end of the previous byte transfer. This functionality

is expressed in the timing specification t6—see Figure 83. I

f a

rite operation is aborted during a byte transfer (CS is brought

high), then that byte cannot be written to the destination register.

Destination registers can be up to 3 bytes wide—see Table 9,

Table 10, Table 11, Table 12, and Table 13. Therefore the first

byte shifted into the serial port at DIN is transferred to the MSB

(most significant byte) of the destination register. If, for example,

the addressed register is 12 bits wide, a 2-byte data transfer

must take place. Because the data is always assumed to be right

justified, in this case the 4 MSBs of the first byte would be

ignored and the 4 LSBs of the first byte written to the ADE776

would be the 4 MSBs of the 12-bit word. Figure 84 illustrates

this example.

DIN

SCLK

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

DB7

DB0

DB7

DB0

Interface Write Timing

Figure 83. Serial

SCLK

DIN

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 84. 12-Bit Serial Write Operation

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