ADE7763ARS datasheet(16/56 Pages) AD

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ADE7763

Rev. A | Page 16 of 56

Zero-crossing detection also drives the ZX flag in the interrupt

status register. An active low in the IRQ output appears if the

corresponding bit in the interrupt enable register is set to Logic 1.

The flag in the interrupt status register and the IRQ output are

set to their default values when reset (RSTSTATUS) is read in

the interrupt status register.

Zero-Crossing Timeout

Zero-crossing detection has an associated timeout register,

ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB)

every 128/CLKIN seconds. The register is reset to its user-

programmed, full-scale value when a zero crossing on Channel 2

is detected. The default power-on value in this register is 0xFFF.

If the internal register decrements to 0 before a zero crossing is

detected and the DISSAG bit in the mode register is Logic 0, the

SAG pin will go active low. The absence of a zero crossing is

also indicated on the IRQ pin if the ZXTO enable bit in the

interrupt enable register is set to Logic 1. Irrespective of the

enable bit setting, the ZXTO flag in the interrupt status register

is always set when the internal ZXTOUT register is

decremented to 0—see the Interrupts section.

The ZXOUT register, Address 0x1D, can be written to and read

from by the user—see the Serial Interface section. The

resolution of the register is 128/CLKIN seconds per LSB;

therefore, the maximum delay for an interrupt is 0.15 seconds

(128/CLKIN × 212).

Figure 33 shows the zero-crossing timeout detection when the

line voltage stays at a fixed dc level for more than CLKIN/128 ×

ZXTOUT seconds.

12-BIT INTERNAL

ZXTOUT

CHANNEL 2

ZXTO

DETECTION

BIT

Figure 33. Zero-Crossing Timeout Detection

PERIOD MEASUREMENT

The ADE7763 provides the period measurement of the line.

The PERIOD register is an unsigned, 16-bit register that is

updated every period and always has an MSB of zero.

When CLKIN = 3.579545 MHz, the resolution of this register is

2.2 ms/LSB, which represents 0.013% when the line frequency is

60 Hz. When the line frequency is 60 Hz, the value of the

period register is approximately 7457d. The length of the register

enables the measurement of line frequencies as low as 13.9 Hz.

The period register is stable at ±1 LSB when the line is established

and the measurement does not change. This filter is associated

with a settling time of 1.8 seconds before the measurement is

stable. See the Calibrating an Energy Meter section for more on

the period register.

POWER SUPPLY MONITOR

The ADE7763 contains an on-chip power supply monitor. The

analog supply (AVDD) is continuously monitored. If the supply

is less than 4 V ± 5%, the ADE7763 will go into an inactive state

and no energy will accumulate. This is useful to ensure correct

device operation during power-up and power-down stages. In

addition, built-in hysteresis and filtering help prevent false

triggering due to noisy supplies.

AVDD

ADE7763

POWER-ON

INACTIVE

STATE

SAG

INACTIVE

ACTIVE

INACTIVE

TIME

Figure 34. On-Chip Power Supply Monitor

As seen in Figure 34, the trigger level is nominally set at 4 V.

The tolerance on this trigger level is about ±5%. The SAG pin

can also be used as a power supply monitor input to the MCU.

The SAG pin goes logic low when the ADE7763 is in its inactive

state. The power supply and decoupling for the part should be

such that the ripple at AVDD does not exceed 5 V ± 5%, as

specified for normal operation.

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