ADE7763ARS datasheet(46/56 Pages) AD

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ADE7763

Rev. A | Page 46 of 56

Serial Read Operation

During a data read operation from the ADE7763, data is shifted

out at the DOUT logic output upon the rising edge of SCLK. As

is the case with the data write operation, a write to the commu-

nication register must precede a data read.

With the ADE7763 in communication mode (CS logic low),

first an 8-bit write to the communication register occurs. The

MSB of this byte transfer is a 0, indicating that the next data

transfer operation is a read. The LSBs of this byte contain the

address of the register that is to be read. The ADE7763 starts

shifting data out of the register upon the next rising edge of

SCLK—see Figure 85. At this point, the DOUT logic output

leaves its high impedance state and starts driving the data bus.

All remaining bits of register data are shifted out upon subse-

quent SCLK rising edges. The serial interface also enters commu-

nication mode as soon as the read is complete. Then, the DOUT

logic output enters a high impedance state upon the falling edge

of the last SCLK pulse. The read operation can be aborted by

bringing the CS logic input high before the data transfer is

complete. The DOUT output enters a high impedance state

upon the rising edge of CS.

When an ADE7763 register is addressed for a read operation,

the entire contents of that register are transferred to the serial

port. This allows the ADE7763 to modify its on-chip register

without the risk of corrupting data during a multibyte transfer.

Note that when a read operation follows a write operation, the

read command (i.e., write to communication register) should

not happen for at least 4 µs after the end of the write operation.

If the read command is sent within 4 µs of the write operation,

the last byte of the write operation could be lost. This timing

constraint is given as timing specification t

SCLK

t10

t13

DB0

DB7

DB0

DB7

t11

DIN

DOUT

t12

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 85. Serial Interface Read Timing

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