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STPMIC1 数据表(PDF) 83 Page - STMicroelectronics |
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STPMIC1 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 140 page  6.3.9 Mask reset LDO control register (LDOS_MRST_CR) Table 33. LDOS_MRST_CR 7 6 5 4 3 2 1 0 reserved MRST_REFDDR MRST_LDO6 MRST_LDO5 MRST_LDO4 MRST_LDO3 MRST_LDO2 MRST_LDO1 R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x1A Type: read/write register Default: 0x00 Description: mask reset LDO control register. Set bit to 1 active mask reset option for selected LDO for next reset power-cycle. It is a single shot option. Register is reset to default in CHECK&LOAD state. Refer to Section 5.4.4 Reset and mask_reset option. [7] Reserved [6] MRST_REFDDR: REFDDR LDO mask reset option 0: inactive 1: Mask reset active for REFDDR [5] MRST_LDO6: LDO6 mask default option 0: inactive 1: mask reset active for LDO6 [4] MRST_LDO5: LDO5 mask default option 0: inactive 1: mask reset active for LDO5 [3] MRST_LDO4: LDO4 mask default option 0: inactive 1: mask reset active for LDO4 [2] MRST_LDO3: LDO3 mask default option 0: inactive 1: mask reset active for LDO3 [1] MRST_LDO2: LDO2 mask default option 0: inactive 1: mask default active for LDO2 [0] MRST_LDO1: LDO1 mask default option 0: inactive 1: mask default active for LDO1 STPMIC1 Control registers DS12792 - Rev 7 page 83/140 |
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