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STPMIC1 数据表(PDF) 95 Page - STMicroelectronics |
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STPMIC1 数据表(HTML) 95 Page - STMicroelectronics |
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95 / 140 page  6.4.8 LDOx ALTERNATE mode control registers (LDOx_ALT_CR) (x=1, 2, 5, 6) Table 45. LDOx_ALT_CR 7 6 5 4 3 2 1 0 reserved VOUT[4:0] reserved ENA R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x35, 0x36, 0x39, 0x3A Type: read/write register Default: 0b0XXXXX0X where X depends on the value programmed in NVM Description: LDOx ALTERNATE mode control registers. Register is set to a default value in CHECK&LOAD. User can write to these registers to control enable and voltage settings of LDOx that are applied to ALTERNATE mode. [7] Reserved [6 :2] VOUT[4:0]: refer to Table 9. LDO output voltage settings [1] reserved [0] ENA: LDOx enable bit 0: LDOx is disabled 1: LDOx is enabled STPMIC1 Power supplies control registers DS12792 - Rev 7 page 95/140 |
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