STPMIC1 datasheet(28/140 Pages) STMICROELECTRONICS

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LDO4 is a fixed output voltage (3.3 V) LDO and it is dedicated to power supply host processor USB PHY. It is able

to automatically switch among 3 power inputs (VIN, VBUSOTG and BSTOUT) to provide a valid output voltage in

all application use cases, for example to support a discharged battery for Li-Ion/Li-PO battery-powered device.

DDR REF is sink/source reference voltage LDO dedicated to power VREF of lpDDR/DDR.

BUCK1 to BUCK4 are 2 MHz synchronous step-down converters optimized for high efficiency. To improve

transient response, converters use an adaptive constant on-time (COT) controller with a nominal switching

frequency of 2 MHz.

In low power (LP) mode, converters operate in hysteretic mode to minimize quiescent current and improve

efficiency while an excellent transient response is being kept.

Buck controller also supports a dynamic voltage scaling (DVS) capability with an active discharge (voltage

tracking) and a switching phase shifting pi/2 mutual synchronization between converters to reduce switching EMI

radiations.

BOOST is a fixed output voltage 5.2 V synchronous step-up converter dedicated to power supply USB ports

(PWR_USB_SW and/or PWR_SW power switches). In addition to support a step-up conversion for battery

applications (to convert VBAT=3.6 V to VBUS= 5.2 V), this boost converter has been enhanced with a special

bypass circuitry with smooth output voltage transitions to comply USB VBUS tolerance when the application is

voltage drop through the PCB from input supply of device to USB port.

PWR_USB_SW is a 500 mA power switch suitable for USB OTG port or USB Type-C DRD. Input is internally

connected to BOOST output. It supports VBUS detection, OCP and the reverse current protection.

PWR_SW is a 1000 mA power switch, that can supply max. 2 USB STD HOST port.

4.2

LDO regulators

4.2.1

LDO regulators - common features

The STPMIC1 has 7 LDO regulators with the following meaning:

•

LDO1, LDO2, LDO5 and LDO6 are general purpose LDOs

•

LDO3 serves for DDR2, DDR3 memory termination (sink-source mode) or for lpDDR2 or lpDDR3 memory

(bypass mode) or for general purpose. For more details refer to Section 4.3 DDR memory sub-system

examples.

•

LDO4 is LDO dedicated to supply 3V3 USB PHY circuit of AP

•

REFDDR – sink/source LDO dedicated to provide a voltage reference for lpDDR/DDR memory

Enable/Disable - LDO can be enabled or disabled:

Automatically during POWER_UP/POWER_DOWN state as described in Section 5.3 POWER_UP,

POWER_DOWN sequence

Manually by setting ENA bit in corresponding Table 40. LDOx_MAIN_CR or Table 45. LDOx_ALT_CR

registers.

VOUT setting – LDO output voltage can be set:

Automatically during POWER_UP/POWER_DOWN state as described in section Section 5.3 POWER_UP,

POWER_DOWN sequence. Default voltage is selected in LDOx_VOUT[1:0] bits of

Table 70. NVM_LDOS_VOUT_SHR1 and Table 71. NVM_LDOS_VOUT_SHR2 registers.

Automatically during MAIN/ALTERNATE mode change by toggling PWRCTRL pin as defined in VOUT[4:0]

field in corresponding Table 40. LDOx_MAIN_CR or Table 45. LDOx_ALT_CR registers.

Manually by setting VOUT[4:0] field of Table 38. BUCKx_MAIN_CR or Table 43. BUCKx_ALT_CR registers.

Refer to Table 9. LDO output voltage settings

STPMIC1

LDO regulators

DS12792 - Rev 7

page 28/140

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