 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STPMIC1 数据表(PDF) 27 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STPMIC1 数据表(HTML) 27 Page - STMicroelectronics |
|
|
27 / 140 page  4 Power regulators and switch description 4.1 Overview The STPMIC1 has a large input voltage range from 2.8 V to 5.5 V to supply applications from typically 5 V DC wall-adaptor or from 1-cell 3.6 V Li-Ion / Li-PO battery or from USB port (bus-powered). The STPMIC1 provides all regulators needed to power supply a complete application: • 6 LDOs + 1 reference voltage LDO for DDR memories • 4 step-down (buck) converters • 1 step-up (boost) converter with a bypass to supply USB sub-system • 2 power switches to supply USB sub-system Table 8. General description Regulator Output voltage (V) Programming step(mV) Rated output current (mA) Application use (example) LDO1 1.7 to 3.3 100 350 GP LDO2 1.7 to 3.3 100 350 SD-card or GP LDO3 normal mode 1.7 to 3.3 100 100 lpDDR_1V8 or GP LDO3 sink/source mode VOUT2 / 2 (BUCK2) - +/-120 (+/-200 peak) DDR3 VTT (termination) LDO3 bypass mode LDO3IN-VDROP_LDO3 - 50 lpDDR_1V8 LDO4 3.3 (fixed) - 50 USB PHY LDO5 1.7 to 3.9 100 350 Application FlashMem or GP LDO6 0.9 to 3.3 100 150 GP REFDDR VOUT2 / 2 (BUCK2) - +/-5 Vref DDR BUCK1 0.725 to 1.5 25 1500 Application CORE BUCK2 1 to 1.5 50 1000 lpDDR2/3/4, DDR3/L, DDR4 BUCK3 1 to 3.4 100 500 Application VIO BUCK4 0.6 to 3.9 25 (0.6 V to 1.3 V) 50 (1.3 V to 1.5 V) 100 (1.5 to 3.9 V) 2000 Application CPU or GP BOOST 5.2 V (fixed) - 1100 USB ports PWR_USB_SW ~BSTOUT - 500 USB OTG/DRD PWR_SW ~SWIN - 1000 USB or GP LDO1, LDO2, LDO5, LDO6 are general purpose (GP) LDO (low-dropout) linear regulators and can be used to supply application peripherals. LDO3 is a multipurpose linear regulator that supports 3 modes: • Normal mode: operates as standard LDO with 1.7 to 3.3 V output voltage range (for general purpose use) • Sink/source mode: LDO3 operates in sink/source regulation mode to supply termination resistors of DDR3/ DDR3L memory interface (VTT voltage) • Bypass mode: LDO3 operates as a simple power switch to supply lpDDR2/3 VDD1 (1.8 V) power domain. In that case, LDO3IN is supplied by 1.8 V. This is a preferred mode versus normal mode in term of power efficiency to power supply lpDDR2/3 VDD1 STPMIC1 Power regulators and switch description DS12792 - Rev 7 page 27/140 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
