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数据搜索系统，热门电子元器件搜索 |
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STPMIC1 数据表(PDF) 3 Page - STMicroelectronics |
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STPMIC1 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 140 page  2 Typical application schematic Figure 1. Typical application schematic christophe belet ST LDO1 LDO2 LDO3 (normal, bypass, DDRVTT) LDO4 LDO5 LDO6 INTLDO BOOST BYPASS PWR_USB_SW PWR_SW SUPPLY MUX VIN DDR_REF (VOUT2/2) VBUSOTG BSTOUT BUCK1IN PGND1 VLX1 VOUT1 CVOUT1 LX1 CBUCK1IN BUCK2IN PGND2 CBUCK2IN BUCK4IN PGND4 CBUCK4IN VLXBST PGND5 CVLXBST BSTOUT CBSTOUT CVBUSOTG VBUSOTG SWOUT LDO3IN VREFDDR LDO3OUT INTLDO CINTLDO CLDO4OUT LDO4OUT CSWOUT CLDO3OUT CLDO3IN CLDO1OUT LDO1OUT CLDO6OUT LDO6OUT CVREF CLDO2OUT LDO2OUT CLDO5OUT LDO5OUT LDO25IN CLDO25IN LDO16IN CLDO16IN SWIN VIN CVIN BUCK3IN PGND3 CBUCK3IN I2C VIO SCL SDA INTn PWRCTRL RSTn WAKEUP PONKEYn LOGIC NVM SYSTEM CONTROL STATE MACHINE POWER SUPPLIES CONTROL REGISTER VLX2 VOUT2 CVOUT2 LX2 VLX3 VOUT3 CVOUT3 LX3 VLX4 VOUT4 CVOUT4 LX4 BUCK1 (SMPS) BUCK2 (SMPS) BUCK3 (SMPS) BUCK4 (SMPS) AGND EPGND user push button LXB VDD_CORE VDD_DDR VDD VDD_AUX (DDR3, DDR3L, lpDDR2, lpDDR3, DDR4) (VIO: 1V8 or 3V3) (to system devices or CPU voltage) (close to USB connector) VBUS_OTG VBUS_HOST VDD_USB (fixed 3.3V to AP USB PHY ) VTT_DDR3 (to DDR3/3L terminations or to lpDDR2/3 VDD1) VREF_DDR VOUT_LDO1 (to system device) VOUT_LDO6 (to system device) VOUT_LDO2 (to Flash Memory or system device) VOUT_LDO5 (to SD-Card or system device) VDD_DDR VDD VIN (VIN from 2.8V to 5.5V DC) VIN close to USB connector) BSTOUT to / from host AP GNDLDO Note: BUCK1IN and BUCK2IN must always be connected to VIN BUCK2IN STPMIC1 Typical application schematic DS12792 - Rev 7 page 3/140 |
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