STPMIC1 datasheet(30/140 Pages) STMICROELECTRONICS

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LDO3 is a multipurpose LDO with 3 operating modes:

Normal mode – LDO works as general purpose LDOs to regulate VOUT only, such as the common

LDO1,2,5 and 6.

Bypass mode – LDO operates as a power switch providing output without any regulation. Note, that in this

mode there is no overcurrent limitation available, and LDO is only protected by its input source capability;

that is typically BUCK3 powering application processor VIO domain at 1.8 V.

This mode can be set by writing to bit BYPASS in Table 41. LDO3_MAIN_CR or Table 46. LDO3_ALT_CR

Table 68. NVM_LDOS_RANK_SHR2.

Important : enabling BYPASS bit in Table 41. LDO3_MAIN_CR or Table 46. LDO3_ALT_CR overrides

normal and sink/source mode

Sink/source mode – LDO is able to regulate voltage in source and sink mode allowing current to flow

to/from output; up to maximum rated current. This mode is dedicated to supply termination of DDR3/DDR3L

memories with fixed output voltage. If LDO3 is used in this mode, LDO3IN should be powered from the

output of BUCK2.

When LDO3 is enabled in this mode, output voltage is fixed and follows VOUT2/2; even during BUCK2

ramp-up and ramp-down phase. Overcurrent limitation works the same way as for the other LDOs, and it is

active for both load current polarities.

This mode can be enabled by setting VOUT[6:2] of Table 41. LDO3_MAIN_CR or Table 46. LDO3_ALT_CR

to 0x1F.

Note:

LDO requires the output capacitor with a low value of ESR and care must be taken during PCB design to

minimize parasitic inductance of the track between this capacitor and the device.

LDO4

It is primarily dedicated to supply 3.3 V circuit of USB analog PHY in AP.

VOUT setting – VOUT is fixed to 3.3 V

Automatic input switching - To guarantee the output voltage for various application scenarios (for example to

support discharged battery for Li-Ion/Li-PO battery powered device) LDO4 can be supplied from 3 power sources:

VIN, VBUSOTG and BSTOUT. The selection among these 3 power inputs is fully automatic, no user intervention

is needed. Internal circuit continuously monitors voltage levels on these pins and selects the input source having

the highest input voltage.

Active input source of LDO4 can be read out from LDO4_SRC[1:0] in Section 6.2.5 Restart status register

(RESTART_SR) status register.

REFDDR LDO (DDR reference voltage)

DDR_REF is sink/source LDO similar to LDO3 sink/source mode LDO but with lower current capability primarily

dedicated to supply VREF pin of lpDDR/DDR memories.

VOUT setting - Output voltage is fixed at VOUT2/2 at any time. Input of REFDDR is internally connected to

BUCK2IN.

In case BUCK2 is enabled/disabled when REFDDR is enabled, output of the REFDDR follows BUCK2 startup/

shutdown waveforms always keeping VOUT2/2.

Overcurrent limit circuit - When short-circuit event occurs, output of the LDO is current-limited and output

voltage decreases, however this LDO cannot trigger interrupt or shutdown the device.

4.2.3

LDO output voltage settings

Table 9. LDO output voltage settings

VOUT[4:0]

LDOx_MAIN/

ALT_CR[6:2]

VOUT[V]

LDO1

VOUT[V]

LDO2

VOUT[V]

LDO3

VOUT[V]

LDO5

VOUT[V]

LDO6

1.7

0.9

1.7

1.1

1.7

1.2

STPMIC1

LDO regulators

DS12792 - Rev 7

page 30/140

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