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STPMIC1 数据表(PDF) 89 Page - STMicroelectronics |
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STPMIC1 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 140 page ![]() 6.4.2 REFDDR MAIN mode control register (REFDDR_MAIN_CR) Table 39. REFDDR_MAIN_CR 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved ENA R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x24 Type: read/write register Default: 0x0000000X where X depends on NVM settings Description: REFDDR, MAIN mode control register. Register is initialized in CHECK&LOAD mode. User can write to this register to control the enable of REFDDR applied to MAIN mode. [7 :1] Reserved [0] ENA: VREF_DDR enable bit 0: VREF_DDR is disabled 1: VREF_DDR is enabled STPMIC1 Power supplies control registers DS12792 - Rev 7 page 89/140 |
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