STPMIC1 datasheet(35/140 Pages) STMICROELECTRONICS

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Figure 44. Buck block diagram

Light low power consumption (HP mode)– To minimize power consumption in low load conditions PFM mode

is implemented. Switching between PFM and PWM mode is smooth, fully automatic, and requires no user

intervention.

Low power mode (LP mode) – If the application remains in low load conditions for longer time, the converter can

be switched to LP mode and minimize quiescent consumption to IQ_ BK_LP. In LP mode, the controller works in

hysteretic PFM mode, and has the following features:

Maximum DC current capability is lower, specified by IOUT. However, also in LP mode, converter is able to

handle peak current load of up to IOUT_LP_PEAK but transient response and accuracy are not guaranteed.

ACCU loop is disabled, which results in a lower VOUT accuracy specified by VOUT1-ACC

PLL is disabled. Converter is in PFM mode, which means pulses are not synced to reference clock

To guarantee the best performance, it is recommended LP mode to be entered only when output load is

below IOUTMAX_LP, LP mode can be entered by setting PREG_MODE bit Table 38. BUCKx_MAIN_CR or

Table 43. BUCKx_ALT_CR registers.

Exit from LP mode - It is recommended that application processor switches from LP mode to HP mode before

it applies full rated load exceeding maximum LP current IOUT_LP. This time is defined as minimum LP to HP

recovery time tLP-HP-BKIf load is increased before this time, buck converter stays in regulation but transient or

accuracy specification may not be guaranteed. Refer to Figure 45. BUCKx LP to HP mode recovery time.

Note:

During POWER_UP sequence, buck is always started in HP mode, with default VOUT configuration defined in

NVM_BUCKx_VOUT[1:0] bits of Table 69. NVM_BUCKS_VOUT_SHR register.

Enable/disable - BUCK can be enabled or disabled:

Automatically during POWER_UP/POWER_DOWN state as described in Section 5.3 POWER_UP,

POWER_DOWN sequence

Manually by setting ENA bit in corresponding Table 38. BUCKx_MAIN_CR or Table 43. BUCKx_ALT_CR

registers

VOUT setting – BUCK output voltage can be set:

Automatically during POWER_UP/POWER_DOWN state as described in Section 5.3 POWER_UP,

POWER_DOWN sequence

Default voltage is selected in BUCKx_VOUT[1:0] bits of Table 69. NVM_BUCKS_VOUT_SHR register.

Automatically during MAIN/ALTERNATE mode change by toggling PWRCTRL pin as defined in VOUT[5:0]

field in corresponding Table 38. BUCKx_MAIN_CR or Table 43. BUCKx_ALT_CR registers.

Manually by setting VOUT[5:0] field of Table 38. BUCKx_MAIN_CR or Table 43. BUCKx_ALT_CR registers.

STPMIC1

Buck converters

DS12792 - Rev 7

page 35/140

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