AD4021BCPZ-R2 datasheet(27/39 Pages) AD

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Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 27 of 39

The AD4020/AD4021/AD4022 configuration register is read

from and written to with a 16-bit SPI instruction. The state of

the fields in the configuration register determine which of the

device features are enabled or disabled (see the Configuration

The 16-bit SPI instructions consist of the 8-bit register access

command (see Table 14) followed by the register data. When

performing register read and write operations, CNV is analogous

to a chip select signal, and CNV must be brought low to access

the configuration register contents. Data on SDI is latched in on

each SCK rising edge. Data is shifted out on SDO on each SCK

falling edge. SDO returns to a high impedance state when CNV

is brought high.

The first bit read on SDI after a CNV falling edge (represented

by WEN in Table 14) must be a 0 to initiate the register access

command. The next bit (R/W) determines whether the instruction

is a write or a read. The following six bits must match the values

for Bit 5 through Bit 0, shown in Table 14, to perform the SPI

read/write.

When performing a write operation, the new register contents

are written over SDI MSB first, and the writeable bits in the

configuration register are updated after the device receives the

full byte. When performing a read operation, the current register

contents are shifted out on SDO, MSB first. Figure 49 and

Figure 50 show timing diagrams for register read and write

operations when using any of the CS modes. Figure 51 shows

the timing diagram for performing a write operation to multiple

devices connected in daisy-chain mode.

devices (see the Daisy-Chain Mode section). To verify the contents

of the configuration register, enable and read the status bits (see

the Status Bits section).

The LSB of the configuration register (Bit 0) is a read only bit

that allows digital hosts to ensure the desired digital interface

mode is selected in the frame immediately following a register

write operation. For digital hosts that are limited to 16-bit SPI

frames (such as some microcontrollers), set this bit accordingly

to ensure SDI is at the desired level on the rising edge of CNV.

For example, set this bit to 1 and/or set the idle state of SDI to 1

when using any of the CS modes.

SPI write instructions can be performed in the same frame as

reading a conversion result. To ensure the conversion is

executed correctly, the CNV signal must obey the timing

requirements for the selected interface mode.

Table 14. Register Access Command

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WEN

R/W

tCYC

tSCK

tSCKL

tSCKH

tSCNVSCK

tSSDISCK

tHSDISCK

tCNVH1

tEN

tHSDO

tDSDO

tDIS

tQUIET22

1THE CNV HIGH TIME MUST FOLLOW THE tCONV SPECIFICATION TO GENERATE A VALID CONVERSION RESULT.

2THE SCK FALLING EDGE TO CNV RISING EDGE DELAY MUST FOLLOW THE tQUIET2 SPECIFICATION TO ENSURE SPECIFIED PERFORMANCE.

3X MEANS DON’T CARE.

D19

D18

D17

D16

D15

D14

D13

D12

SDO

WEN

(0)

R/W

(1)

8-BIT REGISTER ACCESS COMMAND

SDI

SCK

CNV

Figure 49. Register Read Timing Diagram

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