AD4021BCPZ-R2 datasheet(25/39 Pages) AD

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Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 25 of 39

lower bandwidth amplifier can be chosen. The longer acquisition

phase means that a lower RC filter (represented by R and C in

Figure 40 to Figure 42 and Figure 44) cutoff can be used, which

means a noisier amplifier can also be tolerated. A larger value of

R can be used in the RC filter with a corresponding smaller

value of C, reducing amplifier stability concerns without affecting

distortion performance significantly. A larger value of R also

results in reduced dynamic power dissipation in the amplifier.

See Table 10 for details on setting the RC filter bandwidth and

choosing a suitable amplifier.

VOLTAGE REFERENCE INPUT

A 10 μF (X7R, 0805 size) ceramic chip capacitor is appropriate

for the optimum performance of the reference input.

For higher performance and lower drift, use a reference such as

the ADR4550. Using a low power reference such as the ADR3450

can result in a slight decrease in the noise performance. It is

recommended to use a reference buffer, such as the ADA4807-1,

between the reference and the ADC reference input. It is important

to consider the optimum capacitance necessary to keep the

reference buffer stable as well as to meet the minimum ADC

requirement stated previously in this section (that is, a 10 μF

ceramic chip capacitor, CREF).

POWER SUPPLY

The AD4020/AD4021/AD4022 use two power supply pins: a core

supply (VDD) and a digital input/output interface supply (VIO).

VIO allows direct interface with any logic between 1.8 V and

5.5 V. To reduce the number of supplies needed, VIO and VDD

can be tied together for 1.8 V operation. The ADP7118 low noise,

complementary metal-oxide semiconductor (CMOS), low dropout

(LDO) linear regulator is recommended to power the VDD and

VIO pins. The AD4020/AD4021/AD4022 are independent of

power supply sequencing between VIO and VDD. Additionally, the

AD4020/AD4021/AD4022 are insensitive to power supply

rejection variations over a wide frequency range, as shown in

Figure 33.

The AD4020/AD4021/AD4022 automatically power down at the

end of each conversion phase. Therefore, the power scales linearly

with the sampling rate. This feature makes the device ideal for

low sampling rates (even a few samples per second) and battery-

powered applications. Figure 35 shows the AD4020/AD4021/

AD4022 total power dissipation and individual power dissipation

for each rail.

DIGITAL INTERFACE

The AD4020/AD4021/AD4022 digital interface is used to

perform analog to digital conversions and to enable and disable

various features. The AD4020/AD4021/AD4022 are compatible

with SPI, QSPI™, and MICROWIRE digital hosts and DSPs.

SCK must be set with clock polarity (CPOL) = clock phase

(CPHA) = 0. A 3-wire interface using the CNV, SCK, and SDO

signals minimizes wiring connections, which is useful in

applications with digital isolation. A 4-wire interface using the

SDI, CNV, SCK, and SDO signals allows CNV, which initiates

the conversions, to be independent of the readback timing

(SDI). This interface is useful in low jitter sampling or

simultaneous sampling applications. In either 3-wire or 4-wire

CS mode, a busy signal can be enabled to indicate when the

conversion result is ready. The busy signal acts as an interrupt

to the digital host to initiate data readback.

The AD4020/AD4021/AD4022 digital interface also supports

daisy-chaining multiple devices to read back results from

multiple ADCs over a single SPI bus.

Timing diagrams and explanations for each digital interface

mode are given in the CS Mode, 3-Wire Turbo Mode section

through the Daisy-Chain Mode section.

Turbo mode allows the use of slower SPI clock rates by extending

the amount of time available to clock out conversion results.

Turbo mode is enabled by setting the turbo mode enable bit to 1 in

the configuration register (see Table 12), and replaces the busy

indicator feature when enabled. The maximum throughput of

1.8 MSPS for the AD4020 can only be achieved with turbo

mode enabled and a minimum SCK frequency of 71 MHz (see

the Serial Clock Frequency Requirements section). See the CS

Mode, 3-Wire Turbo Mode section, and CS Mode, 4-Wire

Turbo Mode section for descriptions of turbo mode operation.

Status bits can also be clocked out at the end of the conversion

data if the status bits are enabled in the configuration register

(see the Status Bits section).

For isolated systems, the ADuM141D is recommended to

support the 71 MHz SCK frequency required to run the

AD4020 at the full throughput of 1.8 MSPS.

The state of SDO on power-up is either low or high-Z, depending

on the states of CNV and SDI, as shown in Table 11.

Table 11. State of SDO on Power-Up

CNV

SDI

SDO

Low

High-Z

Configuration Register Details

The AD4020/AD4021/AD4022 features are controlled via the

configuration register. The configuration register is eight bits

wide and contains enable bits for the status bits, span compression,

high-Z mode, and turbo mode, as well as an overvoltage detection

flag. 16-bit SPI instructions are used to read from and write to

the contents in the configuration register (see the Configuration

descriptions of each field in the configuration register.

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