AD4021BCPZ-R2 datasheet(8/39 Pages) AD

8 / 39 page

AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 8 of 39

Table 3. Register Read/Write Timing

Parameter

Symbol1

Min

Typ

Max

Unit

READ/WRITE OPERATION

CNV Pulse Width2

tCNVH

SCK Period

tSCK

VIO > 2.7 V

9.8

VIO > 1.7 V

12.3

SCK Low Time

tSCKL

SCK High Time

tSCKH

READ OPERATION

CNV Low to SDO D17 MSB Valid Delay

tEN

VIO > 2.7 V

VIO > 1.7 V

SCK Falling Edge to Data Remains Valid

tHSDO

1.5

SCK Falling Edge to Data Valid Delay

tDSDO

VIO > 2.7 V

7.5

VIO > 1.7 V

10.5

CNV Rising Edge to SDO High Impedance

tDIS

WRITE OPERATION

SDI Valid Setup Time from SCK Rising Edge

tSSDISCK

SDI Valid Hold Time from SCK Rising Edge

tHSDISCK

CNV Rising Edge to SCK Edge Hold Time

tHCNVSCK

CNV Falling Edge to SCK Active Edge Setup Time

tSCNVSCK

See Figure 49 to Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure

62, Figure 64, and Figure 66

For turbo mode, tCNVH must match the tQUIET1 minimum.

Table 4. Achievable Throughput for Different Modes of Operation

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

THROUGHPUT, CS MODE

3-Wire and 4-Wire Turbo Mode

fSCK = 100 MHz, VIO ≥ 2.7 V

1.80

MSPS

fSCK = 80 MHz, VIO < 2.7 V

1.80

MSPS

3-Wire and 4-Wire Turbo Mode and Six Status Bits

fSCK = 100 MHz, VIO ≥ 2.7 V

1.80

MSPS

fSCK = 80 MHz, VIO < 2.7 V

1.67

MSPS

3-Wire and 4-Wire Mode

fSCK = 100 MHz, VIO ≥ 2.7 V

1.61

MSPS

fSCK = 80 MHz, VIO < 2.7 V

1.49

MSPS

3-Wire and 4-Wire Mode and Six Status Bits

fSCK = 100 MHz, VIO ≥ 2.7 V

1.47

MSPS

fSCK = 80 MHz, VIO < 2.7 V

1.34

MSPS

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