AD4021BCPZ-R2 datasheet(18/39 Pages) AD

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AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 18 of 39

THEORY OF OPERATION

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

262,144C

524,288C

LSB

SW+

MSB

LSB

SW–

MSB

262,144C

524,288C

IN+

REF

GND

IN–

Figure 38. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD4020/AD4021/AD4022 are high speed, low power,

single-supply, precise, 20-bit differential ADCs based on a SAR

architecture.

The AD4020 is capable of converting 1,800,000 samples per

second (1.8 MSPS), the AD4021 is capable of converting

1,000,000 samples per second (1 MSPS), and the AD4022 is

capable of converting 500,000 samples per second (500 kSPS).

The power consumption of the AD4020/AD4021/AD4022

scales with throughput because they power down in between

conversions. For example, when operating at 10 kSPS, they

typically consume 83 µW, making them ideal for battery-

powered applications. The AD4020/AD4021/AD4022 also have a

valid first conversion after being powered down for long periods,

which can further reduce power consumed in applications in

which the ADC does not need to be constantly converting.

The AD4020/AD4021/AD4022 provide the user with an on-chip

track-and-hold and do not exhibit any pipeline delay or latency,

making them ideal for multiplexed applications.

The AD4020/AD4021/AD4022 incorporate a multitude of

unique, easy to use features that result in a lower system power

and smaller footprint.

The AD4020/AD4021/AD4022 each have an internal voltage

clamp that protects the device from overvoltage damage on the

analog inputs.

The analog input incorporates circuitry that reduces the nonlinear

charge kickback seen from a typical switched capacitor SAR input.

This reduction in kickback, combined with a longer acquisition

phase, allows the use of lower bandwidth and lower power

amplifiers as drivers. This combination has the additional benefit of

allowing a larger resistor value in the input RC filter and a

corresponding smaller capacitor, which results in a smaller RC load

for the amplifier, improving stability and power dissipation.

High-Z mode can be enabled via the SPI interface by programming

a register bit (see Table 12). When high-Z mode is enabled, the

ADC input has a low input charging current at low input signal

frequencies as well as improved distortion over a wide frequency

range up to 100 kHz. For frequencies greater than 100 kHz and

multiplexing functionality, disable high-Z mode.

For single-supply applications, a span compression feature

creates additional headroom and footroom for the driving

amplifier to access the full range of the ADC.

The fast conversion time of the AD4020/AD4021/AD4022, along

with turbo mode, allows low clock rates to read back conversions

even when running at their respective maximum throughput

rates. Note that, for the AD4020, the full throughput rate of

1.8 MSPS can be achieved only with turbo mode enabled.

The AD4020/AD4021/AD4022 can interface with any 1.8 V to

5 V digital logic family. These devices are available in a 10-lead

MSOP or a tiny 10-lead LFCSP that allows space savings and

flexible configurations.

The AD4020/AD4021/AD4022 are pin for pin compatible with

some of the 14-/16-/18-/20-bit precision SAR ADCs listed in

Table 8.

Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR

ADCs

Bits

100 kSPS

250 kSPS

400 kSPS to

500 kSPS

≥1000 kSPS

201

Not applicable

AD40222

AD40202

AD40212

181

AD7989-12

AD76912

AD7690,2

AD7989-5,2

AD40112

AD4003,2

AD4007,2

AD7982,2

AD79842

161

AD7684

AD7687

AD7688,2

AD76932

AD4001,2

AD4005,2

AD79152

163

AD7680,

AD7683,

AD7988-12

AD7685,2

AD76942

AD7686,2

AD7988-52

AD4000,2

AD4004,2

AD7980,2

AD79832

143

AD7940

AD79422

AD79462

Not applicable

True differential.

Pin for pin compatible.

Pseudo differential.

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