AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 6 of 39

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL OUTPUTS

Data Format

Serial, 20 bits, twos complement

Pipeline Delay

Conversion results available immediately

after completed conversion

Output current = 500 µA

0.4

V

Output current = −500 µA

VIO − 0.3

V

POWER SUPPLIES

VDD

1.71

1.8

1.89

V

VIO

1.71

5.5

V

Standby Current

1.6

µA

Power Dissipation

10 kSPS, high-Z mode disabled

83

µW

500 kSPS, high-Z mode disabled

4.5

5.1

mW

1 MSPS, high-Z mode disabled

8.3

10

mW

1.8 MSPS, high-Z mode disabled

15

19

mW

500 kSPS, high-Z mode enabled

5.7

6.9

mW

1 MSPS, high-Z mode enabled

10.8

13

mW

1.8 MSPS, high-Z mode enabled

19

25

mW

VDD Only

500 kSPS, high-Z mode disabled

2.7

mW

1 MSPS, high-Z mode disabled

5.1

mW

1.8 MSPS, high-Z mode disabled

9.0

mW

REF Only

500 kSPS, high-Z mode disabled

1.6

mW

1 MSPS, high-Z mode disabled

2.9

mW

1.8 MSPS, high-Z mode disabled

5.0

mW

VIO Only

500 kSPS, high-Z mode disabled

0.13

mW

1 MSPS, high-Z mode disabled

0.4

mW

1.8 MSPS, high-Z mode disabled

1.0

mW

Energy per Conversion

8.3

nJ/sample

TEMPERATURE RANGE

Specified Performance

−40

+125

°C

1

The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1.8 MSPS for the

AD4020, 1 MSPS for the AD4021, and 500 kSPS for the AD4022.

2

A throughput rate of 1.8 MSPS can only be achieved with turbo mode enabled and a minimum serial clock (SCK) rate of 71 MHz. Refer to Table 4 for the maximum

achievable throughput for different modes of operation.

3

Transient response is the time required for the ADC to acquire a full-scale input step to ±2 LSB accuracy.

4

The minimum and maximum values are guaranteed by characterization, but not production tested.

5

See the 1/f noise plot in Figure 25.